reg_add.vhd

来自「自己用VHDL写的并行乘法累加和元算」· VHDL 代码 · 共 82 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity reg_add is
     port(clk_reg:in std_logic;
          clr:in std_logic;
          clk_regbt:in std_logic;
          set:in std_logic;
          q0:in std_logic_vector(7 downto 0);
          q1:in std_logic_vector(7 downto 0);
          q2:in std_logic_vector(7 downto 0);
          q3:in std_logic_vector(7 downto 0);
          q4:in std_logic_vector(7 downto 0);
          q5:in std_logic_vector(7 downto 0);
          q6:in std_logic_vector(7 downto 0);
          q7:in std_logic_vector(7 downto 0);
          q8:in std_logic_vector(7 downto 0);
          q9:in std_logic_vector(7 downto 0);
          q10:in std_logic_vector(7 downto 0);
          flag:out std_logic;
          data_yn:out std_logic_vector(7 downto 0));
end reg_add;
architecture one of reg_add is
     --signal add_xn0:std_logic_vector(7 downto 0);
     --signal add_xn1:std_logic_vector(7 downto 0);
     --signal add_xn2:std_logic_vector(7 downto 0);
     --signal add_xn3:std_logic_vector(7 downto 0);
     --signal add_xn4:std_logic_vector(7 downto 0);
     --signal add_xn5:std_logic_vector(7 downto 0);
     --signal add_xn6:std_logic_vector(7 downto 0);
     --signal add_xn7:std_logic_vector(7 downto 0);
     --signal add_xn8:std_logic_vector(7 downto 0);
     --signal add_xn9:std_logic_vector(7 downto 0);
     --signal add_xn10:std_logic_vector(7 downto 0);
     
     signal sum91:std_logic_vector(8 downto 0);
     signal sum92:std_logic_vector(8 downto 0);
     signal sum93:std_logic_vector(8 downto 0);
     signal sum94:std_logic_vector(8 downto 0);
     signal sum95:std_logic_vector(8 downto 0);
     signal sum96:std_logic_vector(8 downto 0);
     signal sum101:std_logic_vector(9 downto 0);
     signal sum102:std_logic_vector(9 downto 0);
     signal sum103:std_logic_vector(9 downto 0);
     signal sum104:std_logic_vector(11 downto 0);

     signal result:std_logic_vector(18 downto 0);
     --signal count:std_logic;
     signal sum:std_logic_vector(18 downto 0);
begin
     
     process(clr,set,clk_regbt,clk_reg)
     begin
        if ((clr or set)='1') then 
              sum<=(others=>'0');
              data_yn<=(others=>'0');
              result<=(others=>'0');
        elsif (clk_reg='1') then 
              data_yn<=result(18 downto 11);
              sum<=(others=>'0');
              --result<=(others=>'0');
              flag<='1';
        elsif clk_regbt='1' then
              flag<='0';
              sum91<=('0'& q0) + ('0' & q1);
              sum92<=('0'& q2) + ('0' & q3);
              sum93<=('0'& q4) + ('0' & q5);
              sum94<=('0'& q6) + ('0' & q7);
              sum95<=('0'& q8) + ('0' & q9);
              sum96<=('0'& q10);
              sum101<=('0'& sum91) + ('0'& sum92);
              sum102<=('0'& sum93) + ('0'& sum94);
              sum103<=('0'& sum95) + ('0'& sum96);
              sum104<=("00"& sum101) + ("00"&sum102) + ("00"&sum103);
              sum<=result + ("0000000" & sum104);
        elsif clk_regbt'event and clk_regbt='0' then
              result<=sum(17 downto 0) & '0';
        end if;
     end process;
end one;