reg_add.tan.summary

来自「自己用VHDL写的并行乘法累加和元算」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 24.681 ns
From           : clk_reg
To             : result[15]
From Clock     : 
To Clock       : clk_regbt
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.234 ns
From           : result[13]
To             : data_yn[2]
From Clock     : clk_regbt
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 16.076 ns
From           : clk_reg
To             : data_yn[7]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -0.269 ns
From           : clk_regbt
To             : result[17]
From Clock     : 
To Clock       : clk_regbt
Failed Paths   : 0

Type           : Clock Setup: 'clk_regbt'
Slack          : N/A
Required Time  : None
Actual Time    : 189.50 MHz ( period = 5.277 ns )
From           : result[3]
To             : result[15]
From Clock     : clk_regbt
To Clock       : clk_regbt
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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