reg_add.fit.summary

来自「自己用VHDL写的并行乘法累加和元算」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Mon Aug 13 09:53:12 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : reg_add
Top-level Entity Name : reg_add
Family : Cyclone II
Device : EP2C5Q208C8
Timing Models : Preliminary
Met timing requirements : N/A
Total logic elements : 242 / 4,608 ( 5 % )
Total registers : 18
Total pins : 101 / 142 ( 71 % )
Total virtual pins : 0
Total memory bits : 0 / 119,808 ( 0 % )
Embedded Multiplier 9-bit elements : 0 / 26 ( 0 % )
Total PLLs : 0 / 2 ( 0 % )