stop_watch.fit.qmsg

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "inst10 Global clock " "Info: Automatically promoted signal \"inst10\" to use Global clock" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { -8 736 800 40 "inst10" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clkdiv5k:inst1\|clkout Global clock " "Info: Automatically promoted some destinations of signal \"clkdiv5k:inst1\|clkout\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "inst10 " "Info: Destination \"inst10\" may be non-global or may not use global clock" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { -8 736 800 40 "inst10" "" } } } }  } 0}  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 3 -1 0 } }  } 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "clrn Global clock " "Info: Automatically promoted some destinations of signal \"clrn\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkdiv100:inst29\|clkout " "Info: Destination \"clkdiv100:inst29\|clkout\" may be non-global or may not use global clock" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkdiv5k:inst1\|clkout " "Info: Destination \"clkdiv5k:inst1\|clkout\" may be non-global or may not use global clock" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 3 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "bcdcnt:inst28\|cn " "Info: Destination \"bcdcnt:inst28\|cn\" may be non-global or may not use global clock" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 4 -1 0 } }  } 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "clkdiv10K_to_1K:inst27\|clkout " "Info: Destination \"clkdiv10K_to_1K:inst27\|clkout\" may be non-global or may not use global clock" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 3 -1 0 } }  } 0}  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { 128 -8 160 144 "clrn" "" } } } }  } 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "clrn " "Info: Pin \"clrn\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { 128 -8 160 144 "clrn" "" } } } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clrn" } } } } { "e:/stop_watch/db/stop_watch_cmp.qrpt" "" { Report "e:/stop_watch/db/stop_watch_cmp.qrpt" Compiler "stop_watch" "UNKNOWN" "V1" "e:/stop_watch/db/stop_watch.quartus_db" { Floorplan "e:/stop_watch/" "" "" { clrn } "NODE_NAME" } "" } } { "e:/stop_watch/stop_watch.fld" "" { Floorplan "e:/stop_watch/stop_watch.fld" "" "" { clrn } "NODE_NAME" } }  } 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Info: Started Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Info: Finished Fast Input/Output/OE register processing" {  } {  } 0}
{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" {  } {  } 0}
{ "Info" "IFSAC_FSAC_START_LUT_IO_RAM_PACKING" "" "Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_IO_RAM_PACKING" "" "Info: Finished moving registers into I/O cells, LUTs, and RAM blocks" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "29 unused 3.30 0 29 0 " "Info: Number of I/O pins in group: 29 (unused VREF, 3.30 VCCIO, 0 input, 29 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 11 33 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  33 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.30V 11 34 " "Info: I/O bank number 3 does not use VREF pins and has 3.30V VCCIO pins. 11 total pin(s) used --  34 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use unused 0 42 " "Info: I/O bank number 4 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}