bcdcnt.v

来自「采用Quartus2编写的电子秒表电路 实现计时、暂停等功能」· Verilog 代码 · 共 47 行

module bcdcnt(dsec, sec,secd,secm,clkin,clrn,cn);
      input clkin,clrn;                //Tclkin = 0. 1s
      output[3:0] dsec,sec,secd,secm; 
      output cn;
      reg cn;
      reg[3:0] dsec,sec,secd,secm;
      always @(posedge clkin or negedge clrn)
         begin
         if (!clrn)            
            begin
              dsec<=0;
              sec<=0;
              secd<=0;
              secm<=0;
            end
          else                  
            begin
              if(secm==9)     
 	            begin
	              secm<=0;
	              if(secd==9)
	                begin
	                  secd<=0; 
	                  if(sec==9)
	                    begin
	                      sec<=0;
	                      if(dsec==5)
	                        begin 
	                          dsec<=0;
	                          cn<=1;
	                        end 
	                      else dsec<=dsec+1;
	                    end
	                  else sec<=sec+1;
	                end            
	               else secd<=secd+1;
                 end
                else 
                  begin 
                    secm<=secm+1;
                    cn<=0;
                  end
              end 
         //if ((dsec[3:0]==5)&&(sec[3:0]==9)&&(secd[3:0]==9)&&(secm[3:0]==9)) cn<=1;
         //else cn<=0;
           end       
endmodule