p7seg.v

来自「采用Quartus2编写的电子秒表电路 实现计时、暂停等功能」· Verilog 代码 · 共 21 行

module p7seg(out,data);
     input [3:0]data ;   //来自BCD计数器的4位数据
     output [6:0] out;   //7段显示器字段输出
                                    // out[6:0]相当于a,b,c,d,e,f,g 
     reg [6:0] out; 
     always @(data )
        case (data)
            4'd0: out <= 7'b1111110 ;
            4'd1: out <= 7'b0110000 ;
            4'd2: out <= 7'b1101101 ;
            4'd3: out <= 7'b1111001 ;
            4'd4: out <= 7'b0110011 ;
            4'd5: out <= 7'b1011011 ;
            4'd6: out <= 7'b1011111 ;
            4'd7: out <= 7'b1110000 ;
            4'd8: out <= 7'b1111111 ;
            4'd9: out <= 7'b1111011 ;
            default:out <= 7'b0000000;
             //当data为4'hA~4'hF时，7段显示器不亮
       endcase
endmodule