stop_watch.map.qmsg

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "button button:inst " "Info: Elaborating entity \"button\" for hierarchy \"button:inst\"" {  } { { "stop_watch.bdf" "inst" { Schematic "e:/stop_watch/stop_watch.bdf" { { 8 264 384 104 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(11) " "Warning: Verilog HDL assignment warning at button.v(11): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/stop_watch/button.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 button.v(13) " "Warning: Verilog HDL assignment warning at button.v(13): truncated value with size 32 to match size of target (7)" {  } { { "button.v" "" { Text "e:/stop_watch/button.v" 13 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv10K_to_1K clkdiv10K_to_1K:inst27 " "Info: Elaborating entity \"clkdiv10K_to_1K\" for hierarchy \"clkdiv10K_to_1K:inst27\"" {  } { { "stop_watch.bdf" "inst27" { Schematic "e:/stop_watch/stop_watch.bdf" { { -56 440 568 40 "inst27" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkdiv10K_to_1K.v(8) " "Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(8): truncated value with size 32 to match size of target (4)" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv10K_to_1K.v(11) " "Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(11): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkdiv10K_to_1K.v(12) " "Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(12): truncated value with size 32 to match size of target (4)" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv10K_to_1K.v(16) " "Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(16): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 clkdiv10K_to_1K.v(17) " "Warning: Verilog HDL assignment warning at clkdiv10K_to_1K.v(17): truncated value with size 32 to match size of target (4)" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 17 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "bcdcnt bcdcnt:inst28 " "Info: Elaborating entity \"bcdcnt\" for hierarchy \"bcdcnt:inst28\"" {  } { { "stop_watch.bdf" "inst28" { Schematic "e:/stop_watch/stop_watch.bdf" { { 160 432 560 288 "inst28" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(11) " "Warning: Verilog HDL assignment warning at bcdcnt.v(11): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(12) " "Warning: Verilog HDL assignment warning at bcdcnt.v(12): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(13) " "Warning: Verilog HDL assignment warning at bcdcnt.v(13): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 13 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(14) " "Warning: Verilog HDL assignment warning at bcdcnt.v(14): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 14 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(20) " "Warning: Verilog HDL assignment warning at bcdcnt.v(20): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 20 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(23) " "Warning: Verilog HDL assignment warning at bcdcnt.v(23): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 23 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(26) " "Warning: Verilog HDL assignment warning at bcdcnt.v(26): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 26 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(29) " "Warning: Verilog HDL assignment warning at bcdcnt.v(29): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 29 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 bcdcnt.v(30) " "Warning: Verilog HDL assignment warning at bcdcnt.v(30): truncated value with size 32 to match size of target (1)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 30 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(32) " "Warning: Verilog HDL assignment warning at bcdcnt.v(32): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 32 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(34) " "Warning: Verilog HDL assignment warning at bcdcnt.v(34): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 34 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(36) " "Warning: Verilog HDL assignment warning at bcdcnt.v(36): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 36 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 bcdcnt.v(40) " "Warning: Verilog HDL assignment warning at bcdcnt.v(40): truncated value with size 32 to match size of target (4)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 40 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 bcdcnt.v(41) " "Warning: Verilog HDL assignment warning at bcdcnt.v(41): truncated value with size 32 to match size of target (1)" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 41 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "p7seg p7seg:inst23 " "Info: Elaborating entity \"p7seg\" for hierarchy \"p7seg:inst23\"" {  } { { "stop_watch.bdf" "inst23" { Schematic "e:/stop_watch/stop_watch.bdf" { { 168 632 776 216 "inst23" "" } } } }  } 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO_POWER_UP_CHANGE" "button:inst\|enable~reg0 button:inst\|signal " "Info: Duplicate register \"button:inst\|enable~reg0\" merged to single register \"button:inst\|signal\", power-up level changed" {  } { { "button.v" "" { Text "e:/stop_watch/button.v" 4 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "186 " "Info: Implemented 186 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "46 " "Info: Implemented 46 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "137 " "Info: Implemented 137 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 37 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 37 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 14 19:32:11 2008 " "Info: Processing ended: Mon Apr 14 19:32:11 2008" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0}  } {  } 0}