stop_watch.map.qmsg

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 14 19:32:08 2008 " "Info: Processing started: Mon Apr 14 19:32:08 2008" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off stop_watch -c stop_watch " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off stop_watch -c stop_watch" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "stop_watch.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file stop_watch.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 stop_watch " "Info: Found entity 1: stop_watch" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bcdcnt.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file bcdcnt.v" { { "Info" "ISGN_ENTITY_NAME" "1 bcdcnt " "Info: Found entity 1: bcdcnt" {  } { { "bcdcnt.v" "" { Text "e:/stop_watch/bcdcnt.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "button.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file button.v" { { "Info" "ISGN_ENTITY_NAME" "1 button " "Info: Found entity 1: button" {  } { { "button.v" "" { Text "e:/stop_watch/button.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "count clkdiv5k.v(4) " "Warning: Verilog HDL warning at clkdiv5k.v(4): using specified range for net, port, or variable \"count\" that was previously declared without a range specification" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 4 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv5k.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv5k.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv5k " "Info: Found entity 1: clkdiv5k" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "count clkdiv10K_to_1K.v(4) " "Warning: Verilog HDL warning at clkdiv10K_to_1K.v(4): using specified range for net, port, or variable \"count\" that was previously declared without a range specification" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 4 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv10K_to_1K.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv10K_to_1K.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv10K_to_1K " "Info: Found entity 1: clkdiv10K_to_1K" {  } { { "clkdiv10K_to_1K.v" "" { Text "e:/stop_watch/clkdiv10K_to_1K.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Warning" "WVRFX_VERI_PREVIOUSLY_DECLARED_WITHOUT_RANGE" "count clkdiv100.v(4) " "Warning: Verilog HDL warning at clkdiv100.v(4): using specified range for net, port, or variable \"count\" that was previously declared without a range specification" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 4 0 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "clkdiv100.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file clkdiv100.v" { { "Info" "ISGN_ENTITY_NAME" "1 clkdiv100 " "Info: Found entity 1: clkdiv100" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "p7seg.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file p7seg.v" { { "Info" "ISGN_ENTITY_NAME" "1 p7seg " "Info: Found entity 1: p7seg" {  } { { "p7seg.v" "" { Text "e:/stop_watch/p7seg.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "stop_watch " "Info: Elaborating entity \"stop_watch\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "NOT inst7 " "Warning: Block or symbol \"NOT\" of instance \"inst7\" overlaps another block or symbol" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { 24 560 608 56 "inst7" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "p7seg inst23 " "Warning: Block or symbol \"p7seg\" of instance \"inst23\" overlaps another block or symbol" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { 168 632 776 216 "inst23" "" } } } }  } 0}
{ "Warning" "WGDFX_SYMBOLS_OVERLAP_WARNING" "p7seg inst25 " "Warning: Block or symbol \"p7seg\" of instance \"inst25\" overlaps another block or symbol" {  } { { "stop_watch.bdf" "" { Schematic "e:/stop_watch/stop_watch.bdf" { { 248 632 776 296 "inst25" "" } } } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv100 clkdiv100:inst29 " "Info: Elaborating entity \"clkdiv100\" for hierarchy \"clkdiv100:inst29\"" {  } { { "stop_watch.bdf" "inst29" { Schematic "e:/stop_watch/stop_watch.bdf" { { -32 856 984 64 "inst29" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clkdiv100.v(8) " "Warning: Verilog HDL assignment warning at clkdiv100.v(8): truncated value with size 32 to match size of target (7)" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv100.v(11) " "Warning: Verilog HDL assignment warning at clkdiv100.v(11): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clkdiv100.v(12) " "Warning: Verilog HDL assignment warning at clkdiv100.v(12): truncated value with size 32 to match size of target (7)" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv100.v(16) " "Warning: Verilog HDL assignment warning at clkdiv100.v(16): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 7 clkdiv100.v(17) " "Warning: Verilog HDL assignment warning at clkdiv100.v(17): truncated value with size 32 to match size of target (7)" {  } { { "clkdiv100.v" "" { Text "e:/stop_watch/clkdiv100.v" 17 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clkdiv5k clkdiv5k:inst1 " "Info: Elaborating entity \"clkdiv5k\" for hierarchy \"clkdiv5k:inst1\"" {  } { { "stop_watch.bdf" "inst1" { Schematic "e:/stop_watch/stop_watch.bdf" { { -224 208 344 -128 "inst1" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 clkdiv5k.v(8) " "Warning: Verilog HDL assignment warning at clkdiv5k.v(8): truncated value with size 32 to match size of target (13)" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 8 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv5k.v(11) " "Warning: Verilog HDL assignment warning at clkdiv5k.v(11): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 11 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 clkdiv5k.v(12) " "Warning: Verilog HDL assignment warning at clkdiv5k.v(12): truncated value with size 32 to match size of target (13)" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 12 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 clkdiv5k.v(16) " "Warning: Verilog HDL assignment warning at clkdiv5k.v(16): truncated value with size 32 to match size of target (1)" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 16 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 clkdiv5k.v(17) " "Warning: Verilog HDL assignment warning at clkdiv5k.v(17): truncated value with size 32 to match size of target (13)" {  } { { "clkdiv5k.v" "" { Text "e:/stop_watch/clkdiv5k.v" 17 0 0 } }  } 0}