stop_watch.hier_info

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能

|stop_watch
clk0 <= clkdiv100:inst29.clkout
clrn => clkdiv100:inst29.clrn
clrn => clkdiv5k:inst1.clrn
clrn => inst8.ACLR
clrn => clkdiv10K_to_1K:inst27.clrn
clrn => bcdcnt:inst28.clrn
clk => clkdiv5k:inst1.clkin
startstopn => button:inst.phn
cn <= bcdcnt:inst28.cn
bin_dsec[0] <= bcdcnt:inst28.dsec[0]
bin_dsec[1] <= bcdcnt:inst28.dsec[1]
bin_dsec[2] <= bcdcnt:inst28.dsec[2]
bin_dsec[3] <= bcdcnt:inst28.dsec[3]
bin_sec[0] <= bcdcnt:inst28.sec[0]
bin_sec[1] <= bcdcnt:inst28.sec[1]
bin_sec[2] <= bcdcnt:inst28.sec[2]
bin_sec[3] <= bcdcnt:inst28.sec[3]
bin_secd[0] <= bcdcnt:inst28.secd[0]
bin_secd[1] <= bcdcnt:inst28.secd[1]
bin_secd[2] <= bcdcnt:inst28.secd[2]
bin_secd[3] <= bcdcnt:inst28.secd[3]
bin_secm[0] <= bcdcnt:inst28.secm[0]
bin_secm[1] <= bcdcnt:inst28.secm[1]
bin_secm[2] <= bcdcnt:inst28.secm[2]
bin_secm[3] <= bcdcnt:inst28.secm[3]
dsec[0] <= p7seg:inst23.out[0]
dsec[1] <= p7seg:inst23.out[1]
dsec[2] <= p7seg:inst23.out[2]
dsec[3] <= p7seg:inst23.out[3]
dsec[4] <= p7seg:inst23.out[4]
dsec[5] <= p7seg:inst23.out[5]
dsec[6] <= p7seg:inst23.out[6]
sec[0] <= p7seg:inst24.out[0]
sec[1] <= p7seg:inst24.out[1]
sec[2] <= p7seg:inst24.out[2]
sec[3] <= p7seg:inst24.out[3]
sec[4] <= p7seg:inst24.out[4]
sec[5] <= p7seg:inst24.out[5]
sec[6] <= p7seg:inst24.out[6]
secd[0] <= p7seg:inst25.out[0]
secd[1] <= p7seg:inst25.out[1]
secd[2] <= p7seg:inst25.out[2]
secd[3] <= p7seg:inst25.out[3]
secd[4] <= p7seg:inst25.out[4]
secd[5] <= p7seg:inst25.out[5]
secd[6] <= p7seg:inst25.out[6]
secm[0] <= p7seg:inst26.out[0]
secm[1] <= p7seg:inst26.out[1]
secm[2] <= p7seg:inst26.out[2]
secm[3] <= p7seg:inst26.out[3]
secm[4] <= p7seg:inst26.out[4]
secm[5] <= p7seg:inst26.out[5]
secm[6] <= p7seg:inst26.out[6]


|stop_watch|clkdiv100:inst29
clrn => count[5]~reg0.ACLR
clrn => count[4]~reg0.ACLR
clrn => count[3]~reg0.ACLR
clrn => count[2]~reg0.ACLR
clrn => count[1]~reg0.ACLR
clrn => count[0]~reg0.ACLR
clrn => count[6]~reg0.ACLR
clrn => clkout~reg0.ENA
clkin => count[5]~reg0.CLK
clkin => count[4]~reg0.CLK
clkin => count[3]~reg0.CLK
clkin => count[2]~reg0.CLK
clkin => count[1]~reg0.CLK
clkin => count[0]~reg0.CLK
clkin => clkout~reg0.CLK
clkin => count[6]~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|stop_watch|clkdiv5k:inst1
clrn => count[11]~reg0.ACLR
clrn => count[10]~reg0.ACLR
clrn => count[9]~reg0.ACLR
clrn => count[8]~reg0.ACLR
clrn => count[7]~reg0.ACLR
clrn => count[6]~reg0.ACLR
clrn => count[5]~reg0.ACLR
clrn => count[4]~reg0.ACLR
clrn => count[3]~reg0.ACLR
clrn => count[2]~reg0.ACLR
clrn => count[1]~reg0.ACLR
clrn => count[0]~reg0.ACLR
clrn => count[12]~reg0.ACLR
clrn => clkout~reg0.ENA
clkin => count[11]~reg0.CLK
clkin => count[10]~reg0.CLK
clkin => count[9]~reg0.CLK
clkin => count[8]~reg0.CLK
clkin => count[7]~reg0.CLK
clkin => count[6]~reg0.CLK
clkin => count[5]~reg0.CLK
clkin => count[4]~reg0.CLK
clkin => count[3]~reg0.CLK
clkin => count[2]~reg0.CLK
clkin => count[1]~reg0.CLK
clkin => count[0]~reg0.CLK
clkin => clkout~reg0.CLK
clkin => count[12]~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[4] <= count[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[5] <= count[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[6] <= count[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[7] <= count[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[8] <= count[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[9] <= count[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[10] <= count[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[11] <= count[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[12] <= count[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|stop_watch|button:inst
clkin => cnt[5]~reg0.CLK
clkin => cnt[4]~reg0.CLK
clkin => cnt[3]~reg0.CLK
clkin => cnt[2]~reg0.CLK
clkin => cnt[1]~reg0.CLK
clkin => cnt[0]~reg0.CLK
clkin => signal~reg0.CLK
clkin => enable~reg0.CLK
clkin => cnt[6]~reg0.CLK
phn => always0~0.IN1
signal <= signal~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[0] <= cnt[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[1] <= cnt[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[2] <= cnt[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[3] <= cnt[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[4] <= cnt[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[5] <= cnt[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
cnt[6] <= cnt[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
enable <= enable~reg0.DB_MAX_OUTPUT_PORT_TYPE


|stop_watch|clkdiv10K_to_1K:inst27
clrn => count[2]~reg0.ACLR
clrn => count[1]~reg0.ACLR
clrn => count[0]~reg0.ACLR
clrn => count[3]~reg0.ACLR
clrn => clkout~reg0.ENA
clkin => count[2]~reg0.CLK
clkin => count[1]~reg0.CLK
clkin => count[0]~reg0.CLK
clkin => clkout~reg0.CLK
clkin => count[3]~reg0.CLK
clkout <= clkout~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[0] <= count[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[1] <= count[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[2] <= count[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
count[3] <= count[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|stop_watch|bcdcnt:inst28
dsec[0] <= dsec[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dsec[1] <= dsec[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dsec[2] <= dsec[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dsec[3] <= dsec[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[0] <= sec[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[1] <= sec[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[2] <= sec[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
sec[3] <= sec[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secd[0] <= secd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secd[1] <= secd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secd[2] <= secd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secd[3] <= secd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secm[0] <= secm[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secm[1] <= secm[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secm[2] <= secm[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
secm[3] <= secm[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
clkin => dsec[2]~reg0.CLK
clkin => dsec[1]~reg0.CLK
clkin => dsec[0]~reg0.CLK
clkin => sec[3]~reg0.CLK
clkin => sec[2]~reg0.CLK
clkin => sec[1]~reg0.CLK
clkin => sec[0]~reg0.CLK
clkin => secd[3]~reg0.CLK
clkin => secd[2]~reg0.CLK
clkin => secd[1]~reg0.CLK
clkin => secd[0]~reg0.CLK
clkin => secm[3]~reg0.CLK
clkin => secm[2]~reg0.CLK
clkin => secm[1]~reg0.CLK
clkin => secm[0]~reg0.CLK
clkin => cn~reg0.CLK
clkin => dsec[3]~reg0.CLK
clrn => dsec[2]~reg0.ACLR
clrn => dsec[1]~reg0.ACLR
clrn => dsec[0]~reg0.ACLR
clrn => sec[3]~reg0.ACLR
clrn => sec[2]~reg0.ACLR
clrn => sec[1]~reg0.ACLR
clrn => sec[0]~reg0.ACLR
clrn => secd[3]~reg0.ACLR
clrn => secd[2]~reg0.ACLR
clrn => secd[1]~reg0.ACLR
clrn => secd[0]~reg0.ACLR
clrn => secm[3]~reg0.ACLR
clrn => secm[2]~reg0.ACLR
clrn => secm[1]~reg0.ACLR
clrn => secm[0]~reg0.ACLR
clrn => dsec[3]~reg0.ACLR
clrn => cn~reg0.ENA
cn <= cn~reg0.DB_MAX_OUTPUT_PORT_TYPE


|stop_watch|p7seg:inst23
out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0


|stop_watch|p7seg:inst24
out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0


|stop_watch|p7seg:inst25
out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0


|stop_watch|p7seg:inst26
out[0] <= reduce_or~6.DB_MAX_OUTPUT_PORT_TYPE
out[1] <= reduce_or~5.DB_MAX_OUTPUT_PORT_TYPE
out[2] <= reduce_or~4.DB_MAX_OUTPUT_PORT_TYPE
out[3] <= reduce_or~3.DB_MAX_OUTPUT_PORT_TYPE
out[4] <= reduce_or~2.DB_MAX_OUTPUT_PORT_TYPE
out[5] <= reduce_or~1.DB_MAX_OUTPUT_PORT_TYPE
out[6] <= reduce_or~0.DB_MAX_OUTPUT_PORT_TYPE
data[0] => Decoder~0.IN3
data[1] => Decoder~0.IN2
data[2] => Decoder~0.IN1
data[3] => Decoder~0.IN0