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📄 stop_watch.map.eqn

📁 采用Quartus2编写的电子秒表电路 实现计时、暂停等功能
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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--G1_clkout is clkdiv100:inst29|clkout
--operation mode is normal

G1_clkout_lut_out = !G1L22;
G1_clkout = DFFEAS(G1_clkout_lut_out, inst10, VCC, , clrn, , , , );


--F1_cn is bcdcnt:inst28|cn
--operation mode is normal

F1_cn_lut_out = F1_cn & (F1L11 # F1L3 & !F1L41) # !F1_cn & F1L3 & (!F1L41);
F1_cn = DFFEAS(F1_cn_lut_out, G1_clkout, VCC, , clrn, , , , );


--F1_dsec[3] is bcdcnt:inst28|dsec[3]
--operation mode is normal

F1_dsec[3]_lut_out = !F1_dsec[3];
F1_dsec[3] = DFFEAS(F1_dsec[3]_lut_out, G1_clkout, clrn, , F1L01, , , , );


--F1_dsec[2] is bcdcnt:inst28|dsec[2]
--operation mode is normal

F1_dsec[2]_lut_out = F1_dsec[1] & (F1_dsec[2] $ F1_dsec[0]) # !F1_dsec[1] & F1_dsec[2] & (F1_dsec[3] # !F1_dsec[0]);
F1_dsec[2] = DFFEAS(F1_dsec[2]_lut_out, G1_clkout, clrn, , F1L3, , , , );


--F1_dsec[1] is bcdcnt:inst28|dsec[1]
--operation mode is normal

F1_dsec[1]_lut_out = F1_dsec[1] & (!F1_dsec[0]) # !F1_dsec[1] & F1_dsec[0] & (F1_dsec[3] # !F1_dsec[2]);
F1_dsec[1] = DFFEAS(F1_dsec[1]_lut_out, G1_clkout, clrn, , F1L3, , , , );


--F1_dsec[0] is bcdcnt:inst28|dsec[0]
--operation mode is normal

F1_dsec[0]_lut_out = !F1_dsec[0];
F1_dsec[0] = DFFEAS(F1_dsec[0]_lut_out, G1_clkout, clrn, , F1L3, , , , );


--F1_sec[3] is bcdcnt:inst28|sec[3]
--operation mode is normal

F1_sec[3]_lut_out = F1_sec[3] & (F1_sec[2] $ F1_sec[1] # !F1_sec[0]) # !F1_sec[3] & F1_sec[2] & F1_sec[1] & F1_sec[0];
F1_sec[3] = DFFEAS(F1_sec[3]_lut_out, G1_clkout, clrn, , F1L4, , , , );


--F1_sec[2] is bcdcnt:inst28|sec[2]
--operation mode is normal

F1_sec[2]_lut_out = !F1_sec[2];
F1_sec[2] = DFFEAS(F1_sec[2]_lut_out, G1_clkout, clrn, , F1L91, , , , );


--F1_sec[1] is bcdcnt:inst28|sec[1]
--operation mode is normal

F1_sec[1]_lut_out = F1_sec[1] & (!F1_sec[0]) # !F1_sec[1] & F1_sec[0] & (F1_sec[2] # !F1_sec[3]);
F1_sec[1] = DFFEAS(F1_sec[1]_lut_out, G1_clkout, clrn, , F1L4, , , , );


--F1_sec[0] is bcdcnt:inst28|sec[0]
--operation mode is normal

F1_sec[0]_lut_out = !F1_sec[0];
F1_sec[0] = DFFEAS(F1_sec[0]_lut_out, G1_clkout, clrn, , F1L4, , , , );


--F1_secd[3] is bcdcnt:inst28|secd[3]
--operation mode is normal

F1_secd[3]_lut_out = F1_secd[3] & (F1_secd[2] $ F1_secd[1] # !F1_secd[0]) # !F1_secd[3] & F1_secd[2] & F1_secd[1] & F1_secd[0];
F1_secd[3] = DFFEAS(F1_secd[3]_lut_out, G1_clkout, clrn, , F1L11, , , , );


--F1_secd[2] is bcdcnt:inst28|secd[2]
--operation mode is normal

F1_secd[2]_lut_out = !F1_secd[2];
F1_secd[2] = DFFEAS(F1_secd[2]_lut_out, G1_clkout, clrn, , F1L52, , , , );


--F1_secd[1] is bcdcnt:inst28|secd[1]
--operation mode is normal

F1_secd[1]_lut_out = F1_secd[1] & (!F1_secd[0]) # !F1_secd[1] & F1_secd[0] & (F1_secd[2] # !F1_secd[3]);
F1_secd[1] = DFFEAS(F1_secd[1]_lut_out, G1_clkout, clrn, , F1L11, , , , );


--F1_secd[0] is bcdcnt:inst28|secd[0]
--operation mode is normal

F1_secd[0]_lut_out = !F1_secd[0];
F1_secd[0] = DFFEAS(F1_secd[0]_lut_out, G1_clkout, clrn, , F1L11, , , , );


--F1_secm[3] is bcdcnt:inst28|secm[3]
--operation mode is normal

F1_secm[3]_lut_out = F1_secm[3] & (F1_secm[2] $ F1_secm[1] # !F1_secm[0]) # !F1_secm[3] & F1_secm[2] & F1_secm[1] & F1_secm[0];
F1_secm[3] = DFFEAS(F1_secm[3]_lut_out, G1_clkout, clrn, , , , , , );


--F1_secm[2] is bcdcnt:inst28|secm[2]
--operation mode is normal

F1_secm[2]_lut_out = !F1_secm[2];
F1_secm[2] = DFFEAS(F1_secm[2]_lut_out, G1_clkout, clrn, , F1L1, , , , );


--F1_secm[1] is bcdcnt:inst28|secm[1]
--operation mode is normal

F1_secm[1]_lut_out = F1_secm[1] & (!F1_secm[0]) # !F1_secm[1] & F1_secm[0] & (F1_secm[2] # !F1_secm[3]);
F1_secm[1] = DFFEAS(F1_secm[1]_lut_out, G1_clkout, clrn, , , , , , );


--F1_secm[0] is bcdcnt:inst28|secm[0]
--operation mode is normal

F1_secm[0]_lut_out = !F1_secm[0];
F1_secm[0] = DFFEAS(F1_secm[0]_lut_out, G1_clkout, clrn, , , , , , );


--D1L5 is p7seg:inst23|reduce_or~47
--operation mode is normal

D1L5 = F1_dsec[1] & (F1_dsec[3]) # !F1_dsec[1] & (F1_dsec[2] $ (F1_dsec[0] & !F1_dsec[3]));


--D1L6 is p7seg:inst23|reduce_or~48
--operation mode is normal

D1L6 = F1_dsec[2] & (F1_dsec[3] # F1_dsec[0] $ F1_dsec[1]) # !F1_dsec[2] & (F1_dsec[1] & F1_dsec[3]);


--D1L7 is p7seg:inst23|reduce_or~49
--operation mode is normal

D1L7 = F1_dsec[2] & (F1_dsec[3]) # !F1_dsec[2] & F1_dsec[1] & (F1_dsec[3] # !F1_dsec[0]);


--D1L4 is p7seg:inst23|out[3]~44
--operation mode is normal

D1L4 = F1_dsec[1] & (F1_dsec[3] # F1_dsec[0] & F1_dsec[2]) # !F1_dsec[1] & (F1_dsec[2] $ (F1_dsec[0] & !F1_dsec[3]));


--D1L3 is p7seg:inst23|out[2]~45
--operation mode is normal

D1L3 = F1_dsec[0] # F1_dsec[1] & (F1_dsec[3]) # !F1_dsec[1] & F1_dsec[2];


--D1L2 is p7seg:inst23|out[1]~46
--operation mode is normal

D1L2 = F1_dsec[0] & (F1_dsec[1] # F1_dsec[2] $ !F1_dsec[3]) # !F1_dsec[0] & (F1_dsec[2] & (F1_dsec[3]) # !F1_dsec[2] & F1_dsec[1]);


--D1L1 is p7seg:inst23|out[0]~47
--operation mode is normal

D1L1 = F1_dsec[1] & !F1_dsec[3] & (!F1_dsec[2] # !F1_dsec[0]) # !F1_dsec[1] & (F1_dsec[2] $ F1_dsec[3]);


--D2L5 is p7seg:inst24|reduce_or~47
--operation mode is normal

D2L5 = F1_sec[1] & (F1_sec[3]) # !F1_sec[1] & (F1_sec[2] $ (F1_sec[0] & !F1_sec[3]));


--D2L6 is p7seg:inst24|reduce_or~48
--operation mode is normal

D2L6 = F1_sec[2] & (F1_sec[3] # F1_sec[0] $ F1_sec[1]) # !F1_sec[2] & (F1_sec[1] & F1_sec[3]);


--D2L7 is p7seg:inst24|reduce_or~49
--operation mode is normal

D2L7 = F1_sec[2] & (F1_sec[3]) # !F1_sec[2] & F1_sec[1] & (F1_sec[3] # !F1_sec[0]);


--D2L4 is p7seg:inst24|out[3]~44
--operation mode is normal

D2L4 = F1_sec[1] & (F1_sec[3] # F1_sec[0] & F1_sec[2]) # !F1_sec[1] & (F1_sec[2] $ (F1_sec[0] & !F1_sec[3]));


--D2L3 is p7seg:inst24|out[2]~45
--operation mode is normal

D2L3 = F1_sec[0] # F1_sec[1] & (F1_sec[3]) # !F1_sec[1] & F1_sec[2];


--D2L2 is p7seg:inst24|out[1]~46
--operation mode is normal

D2L2 = F1_sec[0] & (F1_sec[1] # F1_sec[2] $ !F1_sec[3]) # !F1_sec[0] & (F1_sec[2] & (F1_sec[3]) # !F1_sec[2] & F1_sec[1]);


--D2L1 is p7seg:inst24|out[0]~47
--operation mode is normal

D2L1 = F1_sec[1] & !F1_sec[3] & (!F1_sec[2] # !F1_sec[0]) # !F1_sec[1] & (F1_sec[2] $ F1_sec[3]);


--D3L5 is p7seg:inst25|reduce_or~47
--operation mode is normal

D3L5 = F1_secd[1] & (F1_secd[3]) # !F1_secd[1] & (F1_secd[2] $ (F1_secd[0] & !F1_secd[3]));


--D3L6 is p7seg:inst25|reduce_or~48
--operation mode is normal

D3L6 = F1_secd[2] & (F1_secd[3] # F1_secd[0] $ F1_secd[1]) # !F1_secd[2] & (F1_secd[1] & F1_secd[3]);


--D3L7 is p7seg:inst25|reduce_or~49
--operation mode is normal

D3L7 = F1_secd[2] & (F1_secd[3]) # !F1_secd[2] & F1_secd[1] & (F1_secd[3] # !F1_secd[0]);


--D3L4 is p7seg:inst25|out[3]~44
--operation mode is normal

D3L4 = F1_secd[1] & (F1_secd[3] # F1_secd[0] & F1_secd[2]) # !F1_secd[1] & (F1_secd[2] $ (F1_secd[0] & !F1_secd[3]));


--D3L3 is p7seg:inst25|out[2]~45
--operation mode is normal

D3L3 = F1_secd[0] # F1_secd[1] & (F1_secd[3]) # !F1_secd[1] & F1_secd[2];


--D3L2 is p7seg:inst25|out[1]~46
--operation mode is normal

D3L2 = F1_secd[0] & (F1_secd[1] # F1_secd[2] $ !F1_secd[3]) # !F1_secd[0] & (F1_secd[2] & (F1_secd[3]) # !F1_secd[2] & F1_secd[1]);


--D3L1 is p7seg:inst25|out[0]~47
--operation mode is normal

D3L1 = F1_secd[1] & !F1_secd[3] & (!F1_secd[2] # !F1_secd[0]) # !F1_secd[1] & (F1_secd[2] $ F1_secd[3]);


--D4L5 is p7seg:inst26|reduce_or~47
--operation mode is normal

D4L5 = F1_secm[1] & (F1_secm[3]) # !F1_secm[1] & (F1_secm[2] $ (F1_secm[0] & !F1_secm[3]));


--D4L6 is p7seg:inst26|reduce_or~48
--operation mode is normal

D4L6 = F1_secm[2] & (F1_secm[3] # F1_secm[0] $ F1_secm[1]) # !F1_secm[2] & (F1_secm[1] & F1_secm[3]);


--D4L7 is p7seg:inst26|reduce_or~49
--operation mode is normal

D4L7 = F1_secm[2] & (F1_secm[3]) # !F1_secm[2] & F1_secm[1] & (F1_secm[3] # !F1_secm[0]);


--D4L4 is p7seg:inst26|out[3]~44
--operation mode is normal

D4L4 = F1_secm[1] & (F1_secm[3] # F1_secm[0] & F1_secm[2]) # !F1_secm[1] & (F1_secm[2] $ (F1_secm[0] & !F1_secm[3]));


--D4L3 is p7seg:inst26|out[2]~45
--operation mode is normal

D4L3 = F1_secm[0] # F1_secm[1] & (F1_secm[3]) # !F1_secm[1] & F1_secm[2];


--D4L2 is p7seg:inst26|out[1]~46
--operation mode is normal

D4L2 = F1_secm[0] & (F1_secm[1] # F1_secm[2] $ !F1_secm[3]) # !F1_secm[0] & (F1_secm[2] & (F1_secm[3]) # !F1_secm[2] & F1_secm[1]);


--D4L1 is p7seg:inst26|out[0]~47
--operation mode is normal

D4L1 = F1_secm[1] & !F1_secm[3] & (!F1_secm[2] # !F1_secm[0]) # !F1_secm[1] & (F1_secm[2] $ F1_secm[3]);


--G1L91Q is clkdiv100:inst29|count[4]~reg0
--operation mode is normal

G1L91Q_lut_out = G1L1;
G1L91Q = DFFEAS(G1L91Q_lut_out, inst10, clrn, , , , , , );


--G1L81Q is clkdiv100:inst29|count[3]~reg0
--operation mode is normal

G1L81Q_lut_out = G1L3;
G1L81Q = DFFEAS(G1L81Q_lut_out, inst10, clrn, , , , , , );


--G1L71Q is clkdiv100:inst29|count[2]~reg0
--operation mode is normal

G1L71Q_lut_out = G1L5 & G1L22;
G1L71Q = DFFEAS(G1L71Q_lut_out, inst10, clrn, , , , , , );


--G1L02Q is clkdiv100:inst29|count[5]~reg0
--operation mode is normal

G1L02Q_lut_out = G1L7 & G1L22;
G1L02Q = DFFEAS(G1L02Q_lut_out, inst10, clrn, , , , , , );


--G1L32 is clkdiv100:inst29|reduce_nor~35
--operation mode is normal

G1L32 = G1L91Q # G1L81Q # G1L71Q # !G1L02Q;


--G1L61Q is clkdiv100:inst29|count[1]~reg0
--operation mode is normal

G1L61Q_lut_out = G1L9;
G1L61Q = DFFEAS(G1L61Q_lut_out, inst10, clrn, , , , , , );


--G1L51Q is clkdiv100:inst29|count[0]~reg0
--operation mode is normal

G1L51Q_lut_out = G1L11;
G1L51Q = DFFEAS(G1L51Q_lut_out, inst10, clrn, , , , , , );


--G1L12Q is clkdiv100:inst29|count[6]~reg0
--operation mode is normal

G1L12Q_lut_out = G1L31 & G1L22;
G1L12Q = DFFEAS(G1L12Q_lut_out, inst10, clrn, , , , , , );


--G1L22 is clkdiv100:inst29|reduce_nor~0
--operation mode is normal

G1L22 = G1L32 # !G1L12Q # !G1L51Q # !G1L61Q;


--inst8 is inst8
--operation mode is normal

inst8_lut_out = !inst8;
inst8 = DFFEAS(inst8_lut_out, !B1_signal, clrn, , , , , , );


--C1_clkout is clkdiv5k:inst1|clkout
--operation mode is normal

C1_clkout_lut_out = !C1L34;
C1_clkout = DFFEAS(C1_clkout_lut_out, clk, VCC, , clrn, , , , );


--inst10 is inst10
--operation mode is normal

inst10 = inst8 & C1_clkout;


--F1L11 is bcdcnt:inst28|reduce_nor~113
--operation mode is normal

F1L11 = !F1_secm[2] & !F1_secm[1] & F1_secm[3] & F1_secm[0];


--F1L21 is bcdcnt:inst28|reduce_nor~114
--operation mode is normal

F1L21 = F1_sec[2] # F1_sec[1] # !F1_sec[0] # !F1_sec[3];


--F1L31 is bcdcnt:inst28|reduce_nor~115
--operation mode is normal

F1L31 = F1_secd[2] # F1_secd[1] # !F1_secd[0] # !F1_secd[3];


--F1L3 is bcdcnt:inst28|cn~76
--operation mode is normal

F1L3 = F1L11 & !F1L21 & !F1L31;


--F1L41 is bcdcnt:inst28|reduce_nor~116
--operation mode is normal

F1L41 = F1_dsec[3] # F1_dsec[1] # !F1_dsec[0] # !F1_dsec[2];


--F1L01 is bcdcnt:inst28|dsec[3]~137
--operation mode is normal

F1L01 = F1_dsec[2] & F1_dsec[1] & F1_dsec[0] & F1L3;


--F1L4 is bcdcnt:inst28|cn~78
--operation mode is normal

F1L4 = F1L11 & !F1L31;


--F1L91 is bcdcnt:inst28|sec[2]~126
--operation mode is normal

F1L91 = F1_sec[1] & F1_sec[0] & F1L11 & !F1L31;


--F1L52 is bcdcnt:inst28|secd[2]~114
--operation mode is normal

F1L52 = F1_secd[1] & F1_secd[0] & (F1L11);


--F1L1 is bcdcnt:inst28|add~331
--operation mode is normal

F1L1 = F1_secm[1] & F1_secm[0];


--G1L1 is clkdiv100:inst29|add~106
--operation mode is arithmetic

G1L1_carry_eqn = G1L4;
G1L1 = G1L91Q $ (!G1L1_carry_eqn);

--G1L2 is clkdiv100:inst29|add~108
--operation mode is arithmetic

G1L2 = CARRY(G1L91Q & (!G1L4));


--G1L3 is clkdiv100:inst29|add~111
--operation mode is arithmetic

G1L3_carry_eqn = G1L6;
G1L3 = G1L81Q $ (G1L3_carry_eqn);

--G1L4 is clkdiv100:inst29|add~113
--operation mode is arithmetic

G1L4 = CARRY(!G1L6 # !G1L81Q);


--G1L5 is clkdiv100:inst29|add~116
--operation mode is arithmetic

G1L5_carry_eqn = G1L01;
G1L5 = G1L71Q $ (!G1L5_carry_eqn);

--G1L6 is clkdiv100:inst29|add~118
--operation mode is arithmetic

G1L6 = CARRY(G1L71Q & (!G1L01));


--G1L7 is clkdiv100:inst29|add~121
--operation mode is arithmetic

G1L7_carry_eqn = G1L2;
G1L7 = G1L02Q $ (G1L7_carry_eqn);

--G1L8 is clkdiv100:inst29|add~123
--operation mode is arithmetic

G1L8 = CARRY(!G1L2 # !G1L02Q);


--G1L9 is clkdiv100:inst29|add~126
--operation mode is arithmetic

G1L9_carry_eqn = G1L21;
G1L9 = G1L61Q $ (G1L9_carry_eqn);

--G1L01 is clkdiv100:inst29|add~128
--operation mode is arithmetic

G1L01 = CARRY(!G1L21 # !G1L61Q);


--G1L11 is clkdiv100:inst29|add~131
--operation mode is arithmetic

G1L11 = !G1L51Q;

--G1L21 is clkdiv100:inst29|add~133
--operation mode is arithmetic

G1L21 = CARRY(G1L51Q);


--G1L31 is clkdiv100:inst29|add~136
--operation mode is normal

G1L31_carry_eqn = G1L8;
G1L31 = G1L12Q $ (!G1L31_carry_eqn);


--B1_signal is button:inst|signal
--operation mode is normal

B1_signal_lut_out = !B1L13 & !B1L51 & !B1L71 & !B1L02;
B1_signal = DFFEAS(B1_signal_lut_out, E1_clkout, VCC, , , , , , );


--C1L83Q is clkdiv5k:inst1|count[11]~reg0
--operation mode is normal

C1L83Q_lut_out = C1L1;
C1L83Q = DFFEAS(C1L83Q_lut_out, clk, clrn, , , , , , );


--C1L73Q is clkdiv5k:inst1|count[10]~reg0
--operation mode is normal

C1L73Q_lut_out = C1L3;
C1L73Q = DFFEAS(C1L73Q_lut_out, clk, clrn, , , , , , );


--C1L63Q is clkdiv5k:inst1|count[9]~reg0
--operation mode is normal

C1L63Q_lut_out = C1L5 & C1L34;
C1L63Q = DFFEAS(C1L63Q_lut_out, clk, clrn, , , , , , );


--C1L53Q is clkdiv5k:inst1|count[8]~reg0
--operation mode is normal

C1L53Q_lut_out = C1L7 & C1L34;
C1L53Q = DFFEAS(C1L53Q_lut_out, clk, clrn, , , , , , );


--C1L04 is clkdiv5k:inst1|reduce_nor~83
--operation mode is normal

C1L04 = C1L83Q # C1L73Q # !C1L53Q # !C1L63Q;


--C1L33Q is clkdiv5k:inst1|count[6]~reg0
--operation mode is normal

C1L33Q_lut_out = C1L9;
C1L33Q = DFFEAS(C1L33Q_lut_out, clk, clrn, , , , , , );


--C1L23Q is clkdiv5k:inst1|count[5]~reg0
--operation mode is normal

C1L23Q_lut_out = C1L11;
C1L23Q = DFFEAS(C1L23Q_lut_out, clk, clrn, , , , , , );


--C1L13Q is clkdiv5k:inst1|count[4]~reg0
--operation mode is normal

C1L13Q_lut_out = C1L31;
C1L13Q = DFFEAS(C1L13Q_lut_out, clk, clrn, , , , , , );


--C1L43Q is clkdiv5k:inst1|count[7]~reg0
--operation mode is normal

C1L43Q_lut_out = C1L51 & C1L34;
C1L43Q = DFFEAS(C1L43Q_lut_out, clk, clrn, , , , , , );


--C1L14 is clkdiv5k:inst1|reduce_nor~84
--operation mode is normal

C1L14 = C1L33Q # C1L23Q # C1L13Q # !C1L43Q;


--C1L03Q is clkdiv5k:inst1|count[3]~reg0
--operation mode is normal

C1L03Q_lut_out = C1L71 & C1L34;
C1L03Q = DFFEAS(C1L03Q_lut_out, clk, clrn, , , , , , );


--C1L92Q is clkdiv5k:inst1|count[2]~reg0
--operation mode is normal

C1L92Q_lut_out = C1L91;
C1L92Q = DFFEAS(C1L92Q_lut_out, clk, clrn, , , , , , );


--C1L82Q is clkdiv5k:inst1|count[1]~reg0
--operation mode is normal

C1L82Q_lut_out = C1L12;
C1L82Q = DFFEAS(C1L82Q_lut_out, clk, clrn, , , , , , );


--C1L72Q is clkdiv5k:inst1|count[0]~reg0
--operation mode is normal

C1L72Q_lut_out = C1L32;
C1L72Q = DFFEAS(C1L72Q_lut_out, clk, clrn, , , , , , );


--C1L24 is clkdiv5k:inst1|reduce_nor~85
--operation mode is normal

C1L24 = C1L03Q # !C1L72Q # !C1L82Q # !C1L92Q;


--C1L93Q is clkdiv5k:inst1|count[12]~reg0
--operation mode is normal

C1L93Q_lut_out = C1L52 & C1L34;
C1L93Q = DFFEAS(C1L93Q_lut_out, clk, clrn, , , , , , );


--C1L34 is clkdiv5k:inst1|reduce_nor~86
--operation mode is normal

C1L34 = C1L04 # C1L14 # C1L24 # !C1L93Q;


--B1L1 is button:inst|add~421
--operation mode is arithmetic

B1L1_carry_eqn = B1L8;
B1L1 = B1L32Q $ (B1L1_carry_eqn);

--B1L2 is button:inst|add~423
--operation mode is arithmetic

B1L2 = CARRY(!B1L8 # !B1L32Q);


--B1L82Q is button:inst|cnt[6]~reg0
--operation mode is normal

B1L82Q_lut_out = B1L71;

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