clkdiv5k.v

采用Quartus2编写的电子秒表电路 实现计时、暂停等功能

module clkdiv5k (clrn,clkin,clkout,count); 
     input clrn,clkin;                
     output clkout,count;       
     reg[12:0] count;
     reg clkout;
     always @(posedge clkin or negedge clrn)
        begin
            if (!clrn) count<=0;        // 异步清零！低有效
            else if (count==4999) 
               begin
                   clkout<=1;        // clkout只在计数值为999时为"1"
                   count<=0;
               end
            else 
               begin
                   clkout<=0;        // clkout在其他时候都为"0"
                   count<=count+1;
               end
         end
endmodule