fdwt_all.ssf

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

SIMULATOR_SETTINGS
{
	FOCUS_ENTITY_NAME = |FDWT_ALL;
	ESTIMATE_POWER_CONSUMPTION = OFF;
	GLITCH_INTERVAL = 1ns;
	GLITCH_DETECTION = OFF;
	SIMULATION_COVERAGE = ON;
	CHECK_OUTPUTS = OFF;
	RECOVERY_REMOVAL_DETECTION = OFF;
	SETUP_HOLD_DETECTION = OFF;
	USE_COMPILER_SETTINGS = FDWT_ALL;
	ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS = ON;
	SIMULATION_MODE = FUNCTIONAL;
	START_TIME = 0ns;
	CHANNEL_REDRAW_TIME = 1ns;
}