📄 idwt97_address_r.v
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// Address_OutR = {1'b0, Reg_RH[Address_Width/2-2:0], Reg_RL[Address_Width/2 - 1:0]};
Flag = ~Flag;
end
else begin
if(LowPath) //Low Path
Address_OutR = {2'b01, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b11, Reg_RH[4:0], Reg_RL[4:0]};
// Address_OutR = {1'b1, Reg_RH[Address_Width/2-2:0], Reg_RL[Address_Width/2 - 1:0]};
if(Reg_RH[4:0] == 5'h1F) //31
R_Boundary = 1'b1;
else begin
Reg_RH = Reg_RH + 1;
R_Boundary = 1'b0;
end
Flag = ~Flag;
end
end
//Write Memory Address
if(Address_OutW == 'hFFF) begin
Address_OutW = 12'hFFF;
Change_Mode = 1'b1;
Write_En = 0;
Clr = 1'b0;
End_B = 1'b1;
DWT_Reset = 1'b0;
end
else begin
if(Delay == 15) begin //20
if(HiPath) //save LoPath
Address_OutW = {1'b0, Reg_WH[5:0], Reg_WL[4:0]};
else
Address_OutW = {1'b1, Reg_WH[5:0], Reg_WL[4:0]};
if(Reg_WH[5:0] == 6'h3F) begin //63
if(!HiPath)
Reg_WL = Reg_WL + 1;
HiPath = ~HiPath;
Reg_WH = Reg_WH + 1;
Delay = 7; //12
Write_En = 1;
end
else begin
Delay = 15;
Reg_WH = Reg_WH + 1;
Write_En = 1;
end
end
else begin
// Address_OutW = {Reg_WH, Reg_WL};
Delay = Delay + 1;
Write_En = 0;
end
end
end
end //End 2-D Level
S3: begin
Choose_RW = 1'b1;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_RL = 3;
Reg_RH = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1;
Level_Choose = S3; //Level_Choose == Processing State
L_Boundary = 1'b1;
R_Boundary = 1'b0;
if(End_B) begin
End_B = 1'b0;
Clr = 1'b0;
DWT_Reset = 1'b0;
end
else begin
DWT_Reset = 1'b1; //DWT_Reset == 0 ==> Reset, DWT_Reset == 1 ==> Enable
Clr = 1'b1;
end
Write_En = 1'b0;
Change_Mode = 1'b0;
Delay_Mode = 1'b0;
Delay = 0;
end
else begin
Clr = 1'b1;
Done = 1'b0;
Level_Choose = S3; //Level_Choose == Processing State
//Read Memory Address
if(L_Boundary) begin
if(Flag) begin
Address_OutR = {3'b00_0, Reg_RH[4:0], Reg_RL[3:0]};
if(Reg_RL[3:0] == 0) begin
L_Boundary = 1'b0;
Reg_RL = 0;
Flag = ~Flag;
end
else begin
L_Boundary = 1'b1;
Reg_RL = Reg_RL - 1;
Flag = ~Flag;
end
end
else begin
Address_OutR = {3'b00_1, Reg_RH[4:0], Reg_RL[3:0]};
L_Boundary = 1'b1;
Flag = ~Flag;
end
end
else if(R_Boundary) begin
if(Flag) begin
Address_OutR = {3'b00_0, Reg_RH[4:0], Reg_RL[3:0]};
Reg_RL = Reg_RL - 1;
Flag = ~Flag;
end
else begin
Address_OutR = {3'b00_1, Reg_RH[4:0], Reg_RL[3:0]};
if(Reg_RL == 4'hD) begin
Reg_RL = 2;
Reg_RH = Reg_RH + 1;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
Flag = ~Flag;
end
else
Flag = ~Flag;
end
end
else begin
if(Flag) begin
Address_OutR = {3'b00_0, Reg_RH[4:0], Reg_RL[3:0]};
Flag = ~Flag;
end
else begin
Address_OutR = {3'b00_1, Reg_RH[4:0], Reg_RL[3:0]};
if(Reg_RL[3:0] == 4'hF) begin //15
R_Boundary = 1'b1;
end
else begin
Reg_RL = Reg_RL + 1;
R_Boundary = 1'b0;
end
Flag = ~Flag;
end
end
//Write Memory Address
if(Address_OutW == 12'h3FF) begin
Address_OutW = 12'h3FF;
Change_Mode = 1'b1;
Write_En = 0;
Clr = 1'b0;
End_B = 1'b1;
end
else begin
if(Delay == 15) begin //16
Address_OutW = {2'b00, Reg_WH[4:0], Reg_WL[4:0]};
if(Reg_WL[4:0] == 5'h1F) begin //63
Reg_WH = Reg_WH + 1;
Reg_WL = Reg_WL + 1;
Delay = 7; //8
Write_En = 1;
end
else begin
Delay = 15;
Reg_WL = Reg_WL + 1;
Write_En = 1;
end
end
else begin
Address_OutW = {2'b00, Reg_WH[4:0], Reg_WL[4:0]};
Delay = Delay + 1;
Write_En = 0;
end
end
end
end
S4: begin //2-D 2Level
Choose_RW = 1'b0;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_RL = 0;
Reg_RH = 3;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1;
Level_Choose = S4; //Level_Choose == Processing State
L_Boundary = 1'b1;
R_Boundary = 1'b0;
// Clr = 1'b1;
if(End_B) begin
Clr = 1'b0;
End_B = 1'b0;
DWT_Reset = 1'b0;
end
else begin
DWT_Reset = 1; //DWT_Reset == 0 ==> Reset, DWT_Reset == 1 ==> Enable
Clr = 1'b1;
end
Write_En = 0;
Change_Mode = 1'b0;
LowPath = 1'b1;
HiPath = 1'b1;
end
else begin
Clr = 1'b1;
Done = 1'b0;
Level_Choose = S4; //Level_Choose == Processing State
//Read Memory Address
if(L_Boundary) begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {4'b0000, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0010, Reg_RH[3:0], Reg_RL[3:0]};
if(Reg_RH == 0) begin
L_Boundary = 1'b0;
Reg_RH = 0;
Flag = ~Flag;
end
else begin
L_Boundary = 1'b1;
Reg_RH = Reg_RH - 1;
Flag = ~Flag;
end
// L_Boundary = 1'b1;
// Flag = ~Flag;
end
else begin
if(LowPath)
Address_OutR = {4'b0001, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0011, Reg_RH[3:0], Reg_RL[3:0]};
L_Boundary = 1'b1;
Flag = ~Flag;
end
end
else if(R_Boundary) begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {4'b0000, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0010, Reg_RH[3:0], Reg_RL[3:0]};
Flag = ~Flag;
Reg_RH = Reg_RH - 1;
end
else begin
if(LowPath) //Low Path
Address_OutR = {4'b0001, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0011, Reg_RH[3:0], Reg_RL[3:0]};
if(Reg_RH == 6'h0D) begin
Reg_RH = 2;
if(!LowPath)
Reg_RL = Reg_RL + 1;
LowPath = ~LowPath;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
Flag = ~Flag;
end
else
Flag = ~Flag;
// Reg_RH = Reg_RH + 2;
// Flag = ~Flag;
// if({Reg_RH[4:0], Reg_RL[4:0]} == 'h7FF)
// LowPath = 1'b0;
// L_Boundary = 1'b1;
// R_Boundary = 1'b0;
end
end
else begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {4'b0000, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0010, Reg_RH[3:0], Reg_RL[3:0]};
// Address_OutR = {1'b0, Reg_RH[Address_Width/2-2:0], Reg_RL[Address_Width/2 - 1:0]};
Flag = ~Flag;
end
else begin
if(LowPath) //Low Path
Address_OutR = {4'b0001, Reg_RH[3:0], Reg_RL[3:0]};
else
Address_OutR = {4'b0011, Reg_RH[3:0], Reg_RL[3:0]};
// Address_OutR = {1'b1, Reg_RH[Address_Width/2-2:0], Reg_RL[Address_Width/2 - 1:0]};
if(Reg_RH[3:0] == 4'hF) //16
R_Boundary = 1'b1;
else begin
Reg_RH = Reg_RH + 1;
R_Boundary = 1'b0;
end
Flag = ~Flag;
end
end
//Write Memory Address
if(Address_OutW == 'h3FF) begin
Address_OutW = 12'h3FF;
Change_Mode = 1'b1;
Write_En = 0;
End_B = 1'b1;
Clr = 1'b0;
DWT_Reset = 1'b0;
end
else begin
if(Delay == 15) begin //12
if(HiPath) //save LoPath
Address_OutW = {3'b000, Reg_WH[4:0], Reg_WL[3:0]};
else
Address_OutW = {3'b001, Reg_WH[4:0], Reg_WL[3:0]};
if(Reg_WH[4:0] == 5'h1F) begin //31
if(!HiPath)
Reg_WL = Reg_WL + 1;
HiPath = ~HiPath;
Reg_WH = Reg_WH + 1;
Delay = 7; //4
Write_En = 1;
end
else begin
Delay = 15;
Reg_WH = Reg_WH + 1;
Write_En = 1;
end
end
else begin
// Address_OutW = {Reg_WH, Reg_WL};
Delay = Delay + 1;
Write_En = 0;
end
end
end
end //End 2-D 2Level
default: begin //SEnd
Level_Choose = SEnd;
Change_Mode = 1'b0;
Write_En = 0;
Choose_RW = 1'b0;
Done = 1'b1;
end
endcase
end
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