📄 idwt97_address_r.v
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//`timescale 1ns/10ps
module IDWT97_Address_R(
Clk,
Reset,
Address_OutR,
Address_OutW,
DWT_Reset,
Level_Choose,
Delay_Mode,
Write_En,
Choose_RW,
Done
);
parameter Address_Width = 12; // 12 bits ==> image size = 64*64 = 4096
parameter Line_End = 64;
input Clk;
input Reset;
output [Address_Width-1:0] Address_OutR;
output [Address_Width-1:0] Address_OutW;
output DWT_Reset;
output [2:0] Level_Choose;
output Delay_Mode;
output Write_En;
output Choose_RW;
output Done;
reg [Address_Width-1:0] Address_OutR;
reg [Address_Width-1:0] Address_OutW;
reg DWT_Reset;
reg [2:0] Level_Choose;
reg Delay_Mode;
reg Write_En;
reg Choose_RW;
reg Done;
//Register parameter
reg [2:0] CurrentState;
reg [2:0] NextState;
reg [5:0] Delay;
reg Clr;
reg Flag;
reg L_Boundary;
reg R_Boundary;
reg Change_Mode;
reg LowPath;
reg HiPath;
reg End_B;
reg [Address_Width/2 - 1:0] Reg_WL;
reg [Address_Width/2 - 1:0] Reg_WH;
reg [Address_Width/2 - 1:0] Reg_RL;
reg [Address_Width/2 - 1:0] Reg_RH;
//State
parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;
parameter S4 = 4;
parameter S5 = 5;
parameter S6 = 6;
parameter SEnd = 7;
always @(posedge Clk) begin
if(!Reset)
CurrentState = S0;
else
CurrentState = NextState;
end
always @(CurrentState or Reset or Change_Mode) begin
case(CurrentState)
S0: begin
if(!Reset)
NextState = S0;
else
NextState = S4;
end
S1: begin
if(Change_Mode)
NextState = SEnd;
else
NextState = S1;
end
S2: begin
if(Change_Mode)
NextState = S1;
else
NextState = S2;
end
S3: begin
if(Change_Mode)
NextState = S2;
else
NextState = S3;
end
S4: begin
if(Change_Mode)
NextState = S3;
else
NextState = S4;
end
default: NextState = SEnd;
endcase
end
always @(posedge Clk) begin
case(CurrentState)
S0: begin
Address_OutR = 0;
Address_OutW = 0;
Delay = 0;
Clr = 0;
Flag = 0; //Flag == 0==>Low Path Data, Flag == 1==>Hight Path Data
DWT_Reset = 0; //DWT_Reset == 0 ==> Reset, DWT_Reset == 1 ==> Enable
Level_Choose = S0; //Level_Choose == Processing State
Done = 0; //Done == 0 ==> Processing, Done == 1 ==> End
L_Boundary = 0; //L_Boundary == 0 ==> No porcess Left Boundary, L_Boundary == 1 ==> process Left Boundary
R_Boundary = 0; //R_Boundary == 0 ==> No porcess Right Boundary, R_Boundary == 1 ==> process Right Boundary
Reg_WL = 0; //Count Write Register
Reg_WH = 0; //Count Write Register
Reg_RL = 0; //Count Read Register
Reg_RH = 0; //Count Read Register
Write_En = 0;
Change_Mode = 0;
Delay_Mode = 0;
Choose_RW = 1'b0;
End_B = 1'b0;
end
S1: begin
Choose_RW = 1'b1;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Reg_RL = 3;
Reg_RH = 0;
Reg_WL = 0;
Reg_WH = 0;
Flag = 1;
Level_Choose = S1; //Level_Choose == Processing State
L_Boundary = 1'b1;
R_Boundary = 1'b0;
if(End_B) begin
End_B = 1'b0;
Clr = 1'b0;
DWT_Reset = 1'b0;
end
else begin
Clr = 1'b1;
DWT_Reset = 1'b1; //DWT_Reset == 0 ==> Reset, DWT_Reset == 1 ==> Enable
end
Write_En = 1'b0;
Change_Mode = 1'b0;
Delay_Mode = 1'b0;
// Delay = 0;
end
else begin
Clr = 1'b1;
Done = 1'b0;
Level_Choose = S1; //Level_Choose == Processing State
//Read Memory Address
if(L_Boundary) begin
if(Flag) begin
Address_OutR = {1'b0, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
if(Reg_RL[5:0] == 0) begin
L_Boundary = 1'b0;
Reg_RL = 0;
Flag = ~Flag;
end
else begin
L_Boundary = 1'b1;
Reg_RL = Reg_RL - 1;
Flag = ~Flag;
end
end
else begin
Address_OutR = {1'b1, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
L_Boundary = 1'b1;
Flag = ~Flag;
end
end
else if(R_Boundary) begin
if(Flag) begin
Address_OutR = {1'b0, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
Reg_RL = Reg_RL - 1;
Flag = ~Flag;
end
else begin
Address_OutR = {1'b1, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
if(Reg_RL == 5'h1D) begin
Reg_RL = 2;
Reg_RH = Reg_RH + 1;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
Flag = ~Flag;
end
else
Flag = ~Flag;
end
end
else begin
if(Flag) begin
Address_OutR = {1'b0, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
Flag = ~Flag;
end
else begin
Address_OutR = {1'b1, Reg_RH[Address_Width/2-1:0], Reg_RL[Address_Width/2 - 2:0]};
if(Reg_RL[4:0] == 5'h1F) begin //31
// Reg_RL = Reg_RL - 1;
R_Boundary = 1'b1;
end
else begin
Reg_RL = Reg_RL + 1;
R_Boundary = 1'b0;
end
Flag = ~Flag;
end
end
//Write Memory Address
if(Address_OutW == 'hFFF) begin
Address_OutW = 'hFFF;
Change_Mode = 1'b1;
Write_En = 0;
end
else begin
if(Delay == 15) begin //24
Address_OutW = {Reg_WH, Reg_WL};
if(Reg_WL[5:0] == 6'h3F) begin //63
Reg_WH = Reg_WH + 1;
Reg_WL = Reg_WL + 1;
Delay = 7; //16
Write_En = 1;
end
else begin
Delay = 15;
Reg_WL = Reg_WL + 1;
Write_En = 1;
end
end
else begin
Address_OutW = {Reg_WH, Reg_WL};
Delay = Delay + 1;
Write_En = 0;
end
end
end
end
S2: begin //2-D 1Level
Choose_RW = 1'b0;
if(!Clr) begin
Address_OutR = 0;
Address_OutW = 0;
Flag = 1;
Level_Choose = S2; //Level_Choose == Processing State
L_Boundary = 1'b1;
R_Boundary = 1'b0;
// Clr = 1'b1;
Write_En = 0;
Change_Mode = 1'b0;
LowPath = 1'b1;
HiPath = 1'b1;
Delay = 0;
Reg_RL = 0;
Reg_RH = 3;
Reg_WL = 0;
Reg_WH = 0;
if(End_B) begin
Clr = 1'b0;
End_B = 1'b0;
DWT_Reset = 1'b0;
end
else begin
DWT_Reset = 1; //DWT_Reset == 0 ==> Reset, DWT_Reset == 1 ==> Enable
Clr = 1'b1;
end
end
else begin
Clr = 1'b1;
Done = 1'b0;
Level_Choose = S2; //Level_Choose == Processing State
//Read Memory Address
if(L_Boundary) begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {2'b00, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b10, Reg_RH[4:0], Reg_RL[4:0]};
if(Reg_RH == 0) begin
L_Boundary = 1'b0;
Reg_RH = 0;
Flag = ~Flag;
end
else begin
L_Boundary = 1'b1;
Reg_RH = Reg_RH - 1;
Flag = ~Flag;
end
// L_Boundary = 1'b1;
// Flag = ~Flag;
end
else begin
if(LowPath)
Address_OutR = {2'b01, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b11, Reg_RH[4:0], Reg_RL[4:0]};
L_Boundary = 1'b1;
Flag = ~Flag;
end
end
else if(R_Boundary) begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {2'b00, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b10, Reg_RH[4:0], Reg_RL[4:0]};
Flag = ~Flag;
Reg_RH = Reg_RH - 1;
end
else begin
if(LowPath) //Low Path
Address_OutR = {2'b01, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b11, Reg_RH[4:0], Reg_RL[4:0]};
if(Reg_RH == 5'h1D) begin
Reg_RH = 2;
if(!LowPath)
Reg_RL = Reg_RL + 1;
LowPath = ~LowPath;
L_Boundary = 1'b1;
R_Boundary = 1'b0;
Flag = ~Flag;
end
else
Flag = ~Flag;
// Reg_RH = Reg_RH + 2;
// Flag = ~Flag;
// if({Reg_RH[4:0], Reg_RL[4:0]} == 'h7FF)
// LowPath = 1'b0;
// L_Boundary = 1'b1;
// R_Boundary = 1'b0;
end
end
else begin
if(Flag) begin
if(LowPath) //Low Path
Address_OutR = {2'b00, Reg_RH[4:0], Reg_RL[4:0]};
else
Address_OutR = {2'b10, Reg_RH[4:0], Reg_RL[4:0]};
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