add.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 63 行

//`timescale 1ns/10ps
module Add(
	InData_1,
	InData_2,
	
	OutData
);

parameter Data_Width = 20;

input	[Data_Width-1:0]	InData_1;
input	[Data_Width-1:0]	InData_2;
         
output	[Data_Width-1:0]	OutData;

reg	[Data_Width-1:0]	OutData;
reg	[Data_Width-2:0]	temp;

always @(InData_1 or InData_2) begin
	case({InData_1[Data_Width-1], InData_2[Data_Width-1]})
		// + +
		2'b00: begin
			temp = InData_1[Data_Width-2:0] + InData_2[Data_Width-2:0];
			OutData = {1'b0, temp};
		end
		
		// + -
		2'b01: begin
			if(InData_1[Data_Width-2:0] == InData_2[Data_Width-2:0])
				OutData = 0;
			else if(InData_1[Data_Width-2:0] > InData_2[Data_Width-2:0]) begin
				temp = (InData_1[Data_Width-2:0] + (~InData_2[Data_Width-2:0]) + 1'b1);
				OutData = {1'b0, temp};
			end
			else begin
				temp = (~InData_1[Data_Width-2:0] + InData_2[Data_Width-2:0] + 1'b1);
				OutData = {1'b1, temp};
			end
		end
		
		// - +
		2'b10: begin
			if(InData_1[Data_Width-2:0] == InData_2[Data_Width-2:0])
				OutData = 0;
			else if(InData_1[Data_Width-2:0] > InData_2[Data_Width-2:0]) begin
				temp = (InData_1[Data_Width-2:0] + (~InData_2[Data_Width-2:0]) + 1'b1);
				OutData = {1'b1, temp};
			end
			else begin
				temp = (~InData_1[Data_Width-2:0] + InData_2[Data_Width-2:0] + 1'b1);
				OutData = {1'b0, temp};
			end
		end
		
		// - -
		default: begin
			temp = InData_1[Data_Width-2:0] + InData_2[Data_Width-2:0];
			OutData = {1'b1, temp};
		end
	endcase
end

endmodule