fdwt97_address_r.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

//`timescale 1ns/10ps
module FDWT97_Address_R(
	Clk,
	Reset,
	
	Address_OutR,
	Address_OutW,
	DWT97_Reset,
	Level_Choose,
	Delay_Mode,
	Write_En,
	Choose_RW,
	Done
	);

parameter Address_Width = 12;	// 12 bits ==> image size = 64*64 = 4096
parameter Line_End = 64;

input	Clk;
input	Reset;

output	[Address_Width-1:0]	Address_OutR;
output	[Address_Width-1:0]	Address_OutW;
output				DWT97_Reset;
output	[2:0]			Level_Choose;
output				Delay_Mode;
output				Write_En;
output				Choose_RW;
output				Done;

reg	[Address_Width-1:0]	Address_OutR;
reg	[Address_Width-1:0]	Address_OutW;
reg				DWT97_Reset;
reg	[2:0]			Level_Choose;
reg				Delay_Mode;
reg				Write_En;
reg				Choose_RW;
reg				Done;

//Register parameter
reg	[2:0]			CurrentState;
reg	[2:0]			NextState;
reg	[4:0]			Delay;
reg				Clr;
reg				Flag;
reg				L_Boundary;
reg				R_Boundary;
reg	[Address_Width/2:0]	Reg_WL;
reg	[Address_Width/2:0]	Reg_WH;
reg	[Address_Width/2:0]	Reg_RH;
reg	[Address_Width/2:0]	Reg_RL;
reg				Chang_Mode;
reg				LowPath;
reg				HiPath;
reg				End_B;

//State
parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;
parameter S4 = 4;
parameter S5 = 5;
parameter S6 = 6;
parameter SEnd = 7;


always @(posedge Clk) begin
	if(!Reset)
		CurrentState = S0;
	else
		CurrentState = NextState;
end

always @(CurrentState or Reset or Chang_Mode) begin
	case(CurrentState)
		S0: begin
			if(!Reset)
				NextState = S0;
			else
				NextState = S1;
		end
		
		S1: begin
			if(Chang_Mode)
				NextState = S2;
			else
				NextState = S1;
		end
		
		S2: begin
			if(Chang_Mode)
				NextState = S3;
			else
				NextState = S2;
		end
		
		S3: begin
			if(Chang_Mode)
				NextState = S4;
			else
				NextState = S3;
		end
		
		S4: begin
			if(Chang_Mode)
				NextState = SEnd;
			else
				NextState = S4;
		end
		
		S5: begin
			if(Chang_Mode)
				NextState = SEnd;
			else
				NextState = S5;
		end
		
		S6: begin
			if(Chang_Mode)
				NextState = SEnd;
			else
				NextState = S6;
		end
		
		default: begin
			NextState = SEnd;
		end
		
	endcase
end

always @(posedge Clk) begin
	case(CurrentState)
		S0: begin

		Delay		= 0;       
		Clr		= 0;         
		Flag		= 0;        
		L_Boundary	= 0;  
		R_Boundary	= 0;  
		Reg_WL		= 0;
		Reg_WH		= 0;
		Reg_RH		= 0;       
		Reg_RL		= 0;
		Address_OutR	= 0;
		Address_OutW	= 0;
		DWT97_Reset	= 1'b0;
		Chang_Mode	= 1'b0;
		Write_En	= 1'b0;
		Done		= 1'b0;
		End_B		= 1'b0;
		Level_Choose	= S0;
		Choose_RW	= 1'b0;
		end
		
		S1: begin
			Level_Choose	= S1;
			DWT97_Reset	= 1'b1;
			Choose_RW	= 1'b0;
			if(!Clr) begin
				Address_OutR	= 0;
				Address_OutW 	= 0;
				Reg_WL	     	= 0;
				Reg_WH	     	= 0;
				Flag 	     	= 1;	//LowPath
				Reg_RH	     	= 0;
				Reg_RL	     	= 5;
				L_Boundary   	= 1'b1;
				R_Boundary   	= 1'b0;
				if(End_B) begin
					End_B = ~End_B;
					Clr   = 1'b0;
				end
				else
					Clr = 1;
				DWT97_Reset  	= 1'b1;
				Chang_Mode   	= 1'b0;
				Delay_Mode 	= 1'b0;
				Done	     	= 1'b0;
				Write_En	= 1'b0;
				End_B		= 1'b0;
			end
			else begin
				Clr = 1'b1;
				Address_OutR = {Reg_RH[5:0], Reg_RL[5:0]};
				//Read Memory Address
				if(L_Boundary) begin
					if(Reg_RL==0) begin
						Reg_RL = Reg_RL + 1;
						L_Boundary = 1'b0;
						Delay_Mode = 1'b0;
					end
					else begin
						if(Delay_Mode)
							Delay_Mode = 1'b0;
						Reg_RL = Reg_RL - 1;
						L_Boundary = 1'b1;
					end
				end
				else if(R_Boundary)begin
					
					if({Reg_RH[5:0], Reg_RL[5:0]} == 12'hFFF) begin
						Reg_RL = 6'h3F;
						Reg_RH = 6'h3F;
						R_Boundary = 1'b1;
						L_Boundary = 1'b0;
						
					end
					else begin
						if(Reg_RL == (Line_End - 5)) begin
							Reg_RL = 4;
							Reg_RH = Reg_RH + 1;
							R_Boundary = 1'b0;
							L_Boundary = 1'b1;
							Delay_Mode = 1'b0;
						end
						else begin
							Reg_RL = Reg_RL - 1;
							R_Boundary = 1'b1;
							L_Boundary = 1'b0;
							Delay_Mode = 1'b0;
						end
					end
				end
				else begin
					Delay_Mode = 1'b0;
					if(Reg_RL[5:0] == (Line_End-1)) begin
						R_Boundary = 1'b1;
						Reg_RL = Reg_RL - 1;
					end
					else
						Reg_RL = Reg_RL + 1;
				end

				//Write Memory Address
				if(Address_OutW == 'hFFF) begin
						Address_OutW = 'hFFF;
						Delay = 0;
						Clr = 1'b0;
						End_B = 1'b1;
						DWT97_Reset  = 1'b0;
						Chang_Mode = 1'b1;
						Write_En = 1'b0;
					end
				else begin
					Chang_Mode = 1'b0;
					if(Delay == 15) begin
						if(Flag) begin	//if Flag == 1, ==> save Low Data
							Address_OutW = {1'b0, Reg_WH[5:0], Reg_WL[4:0]};
							Write_En = 1'b1;
							Flag = ~Flag;
						end	// Flag == 1 ==> End

						else begin	//if Flag == 0, ==> save High Data
							Write_En = 1'b1;
							Address_OutW = {1'b1, Reg_WH[5:0], Reg_WL[4:0]};
							if(Reg_WL[4:0] == 5'h1F) begin //if HiPath == 31
								Delay = 7;
//								End_B = 1'b1;
								Flag = ~Flag;
							end
							else begin
								Delay = 15;
//								End_B = 1'b0;
								Flag = ~Flag;
							end

							if(Reg_WL[4:0] == ((Line_End>>1)-1)) begin
								Reg_WH = Reg_WH + 1;
								Write_En = 1'b1;
								Reg_WL = 0;
							end
							else							
								Reg_WL = Reg_WL + 1;
							
						end		//Flag == 0 ==> End
					end
					else begin
						Write_En = 1'b0;
						Delay = Delay + 1;
						Address_OutW = {1'b1, Reg_WH[5:0], Reg_WL[4:0]};
					end
				end
				end	//Address_OutW End
		end//S1 End

		S2: begin	//2D-1Level
			Level_Choose	= S2;
			Choose_RW	= 1'b1;
			if(!Clr) begin
				Address_OutR	= 0;
				Address_OutW 	= 0;
				Reg_WL	     	= 0;
				Reg_WH	     	= 0;
				Reg_RH	     	= 6;
				Reg_RL	     	= 0;
				Flag 	     	= 1;	//LowPath
				L_Boundary   	= 1'b1;
				R_Boundary   	= 1'b0;
				if(End_B) begin
					End_B = ~End_B;
					Clr   = 1'b0;
				end
				else
					Clr = 1;
				
				DWT97_Reset  	= 1'b0;
				Chang_Mode   	= 1'b0;
				Delay_Mode 	= 1'b0;
				Done	     	= 1'b0;
				Write_En	= 1'b0;
//				End_B		= 1'b0;
				LowPath		= 1'b1;	//LL-Path
				HiPath		= 1'b1; //Hi-Path
			end
			else begin
//				Delay_Mode  = 1'b0;
				DWT97_Reset = 1'b1;
				Clr = 1'b1;
				if(LowPath)
					Address_OutR = {1'b0, Reg_RH[5:0], Reg_RL[4:0]};	//Low Path
				else
					Address_OutR = {1'b1, Reg_RH[5:0], Reg_RL[4:0]};	//Hi Path
				//Read Memory Address
				if(L_Boundary) begin
					if(Reg_RH == 0) begin
						Reg_RH = Reg_RH + 1;
						L_Boundary = 1'b0;
						R_Boundary = 1'b0;
						Delay_Mode = 1'b0;
					end
					else begin
						if(Delay_Mode)
							Delay_Mode = 1'b0;
						Reg_RH = Reg_RH - 1;
						L_Boundary = 1'b1;
						R_Boundary = 1'b0;
					end
				end
				else if(R_Boundary)begin
					
					if(Address_OutR == 12'hFFF) begin
						Address_OutR = 12'hFFF;
//						Reg_RL = 6'h3F;
//						Reg_RH = 6'h3F;
						R_Boundary = 1'b1;
						L_Boundary = 1'b0;
					end
					else begin
						if(Reg_RH[5:0] == 6'h3C) begin
							//Hi Path		
							if(LowPath) begin
								LowPath = ~LowPath;
								Reg_RH = 7;
								R_Boundary = 1'b0;
								L_Boundary = 1'b1;
								Delay_Mode = 1'b0;
							end
							else begin
								LowPath = ~LowPath;
								Reg_RH = 5;
								Reg_RL = Reg_RL + 1;
								R_Boundary = 1'b0;
								L_Boundary = 1'b1;
								Delay_Mode = 1'b0;
							end
						end
						else
							Reg_RH = Reg_RH - 1;
							R_Boundary = 1'b1;
					end
				end
				else begin
					Delay_Mode = 1'b0;
					if(Reg_RH[5:0] == 6'h3F) begin
						R_Boundary = 1'b1;
						Reg_RH = Reg_RH - 1;
					end
					else
						Reg_RH = Reg_RH + 1;
				end

				//Write Memory Address
				if(Address_OutW == 'hFFF) begin
						Address_OutW = 'hFFF;
						Delay = 0;
						End_B = 1;
						DWT97_Reset  = 1'b0;
						Chang_Mode = 1'b1;
						Write_En = 1'b0;
						Clr = 1'b0;
					end
				else begin
					Chang_Mode = 1'b0;
					if(Delay == 16) begin	//14
						if(Flag) begin	//if Flag == 1, ==> save Low Data
							if(HiPath)	//Save Low Path
								Address_OutW = {2'b00, Reg_WH[4:0], Reg_WL[4:0]};
							else
								Address_OutW = {2'b10, Reg_WH[4:0], Reg_WL[4:0]};
							Write_En = 1'b1;
							Flag = ~Flag;
						end	// Flag == 1 ==> End

						else begin	//if Flag == 0, ==> save High Data
							Write_En = 1'b1;
							if(HiPath)
								Address_OutW = {2'b01, Reg_WH[4:0], Reg_WL[4:0]};
							else
								Address_OutW = {2'b11, Reg_WH[4:0], Reg_WL[4:0]};

							if(Reg_WH[4:0] == 5'h1F) begin //if HiPath == 31
								if(HiPath)
									Delay = 6;	//4
								else
									Delay = 8;	//6
//								End_B = 1'b1;
								Flag = ~Flag;
							end
							else begin
								Delay = 16;
//								End_B = 1'b0;
								Flag = ~Flag;
							end

							if(Reg_WH[4:0] == 5'h1F) begin
								if(HiPath) begin
									HiPath = ~HiPath;
									Write_En = 1'b1;
									Reg_WH = 0;
								end
								else begin
									HiPath = ~HiPath;
									Reg_WL = Reg_WL + 1;
									Write_En = 1'b1;
									Reg_WH = 0;
								end
							end
							else							
								Reg_WH = Reg_WH + 1;
							
						end		//Flag == 0 ==> End
					end
					else begin
						Write_En = 1'b0;
						Delay = Delay + 1;
//						Address_OutW = {1'b1, Reg_WH[4:0], Reg_WL[5:0]};
//						if(End_B)
//							End_B = ~End_B;
					end
				end
				end	//Address_OutW End
		end//S2 End

		S3: begin
			Level_Choose	= S3;
			Choose_RW	= 1'b0;
			if(!Clr) begin
				Address_OutR	= 0;
				Address_OutW 	= 0;
				Reg_WL	     	= 0;
				Reg_WH	     	= 0;
				Flag 	     	= 1;	//LowPath
				Reg_RH	     	= 0;
				Reg_RL	     	= 6;
				L_Boundary   	= 1'b1;
				R_Boundary   	= 1'b0;
				if(End_B) begin
					End_B = ~End_B;
					Clr   = 1'b0;
				end
				else
					Clr = 1;
				DWT97_Reset  	= 1'b0;
				Chang_Mode   	= 1'b0;
				Delay_Mode 	= 1'b0;
				Done	     	= 1'b0;
				Write_En	= 1'b0;
			end
			else begin
				DWT97_Reset = 1'b1;
				Clr = 1'b1;
				Address_OutR = {2'h0, Reg_RH[4:0], Reg_RL[4:0]};	//31,31
				//Read Memory Address
				if(L_Boundary) begin
					if(Reg_RL==0) begin
						Reg_RL = Reg_RL + 1;
						L_Boundary = 1'b0;
						Delay_Mode = 1'b0;
					end
					else begin
						if(Delay_Mode)
							Delay_Mode = 1'b0;
						Reg_RL = Reg_RL - 1;
						L_Boundary = 1'b1;
					end
				end
				else if(R_Boundary)begin
					
					if({2'h0, Reg_RH[4:0], Reg_RL[4:0]} == 12'h3FF) begin
						Reg_RL = 5'h1F;
						Reg_RH = 5'h1F;
						R_Boundary = 1'b1;
						L_Boundary = 1'b0;
						
					end
					else begin
						if(Reg_RL[4:0] == 5'h1B) begin
							Reg_RL = 4;
							Reg_RH = Reg_RH + 1;
							R_Boundary = 1'b0;
							L_Boundary = 1'b1;
							Delay_Mode = 1'b0;
						end
						else begin
							Reg_RL = Reg_RL - 1;
							R_Boundary = 1'b1;
							L_Boundary = 1'b0;
							Delay_Mode = 1'b0;
						end
					end
				end
				else begin
					Delay_Mode = 1'b0;
					if(Reg_RL[4:0] == 5'h1F) begin
						R_Boundary = 1'b1;
						Reg_RL = Reg_RL - 1;