📄 fdwt_all.csf.msg

📁 這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

💻 MSG

📖 第 1 页 / 共 5 页

字号:

 " "Verilog Design File information: Continuing analyzing of source file \"PctoFPGA.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"FDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"FDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"F:\\Program_Back\\Verilog\\DWT\\OK_PC\\97_2D_1Level\\FPGA\\FDWT_ALL.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"IDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"IDWT97_TOP.v\"
" {  } {  }  }
{  Info "IVLGX_GENERIC0" "Continuing analyzing of source file \"IDWT97_TOP.v\"
 " "Verilog Design File information: Continuing analyzing of source file \"IDWT97_TOP.v\"

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