fdwt97_control.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 106 行

//`timescale 1ns/10ps
module FDWT97_Control(
	Clk,
	Reset,
	Delay_Mode,
	
	Sel
	);

input Clk;
input Reset;
input Delay_Mode;

output [4:0] Sel;


reg [3:0] CurrentState;
reg [3:0] NextState;


reg	A0;
reg	A1;
reg	A2;
reg	A3;
reg	A4;

parameter S0 = 0;
parameter S1 = 1;
parameter S2 = 2;
parameter S3 = 3;

assign Sel = {A4,A3,A2,A1,A0};


always @(posedge Clk) begin
	if(!Reset)
		CurrentState = S0;
	else
		CurrentState = NextState;
end


always @(CurrentState or Reset or Delay_Mode) begin
	case(CurrentState)
		S0: begin
			if(!Reset)
				NextState = S0;
			else
				NextState = S1;
		end
		
		S1: begin
			if(Delay_Mode)
				NextState = S1;
			else
			 	NextState = S2;
		end
		S2: begin
			if(Delay_Mode)
				NextState = S2;
			else
			 	NextState = S1;
		end
		default: begin
			if(Delay_Mode)
				NextState = S3;
			else
				NextState = S1;
		end
		
	endcase
end

always @(CurrentState) begin
	case(CurrentState)
		S0: begin
			A4 = 0;
			A3 = 0;
			A2 = 0;
			A1 = 0;
			A0 = 0;
		end

		S1: begin
			A4 = 1;
			A3 = 1;
			A2 = 0;
		end
		S2:begin
			A4 = 0;
			A3 = 0;
			A2 = 1;
		end

		default: begin
			A4 = 1;
			A3 = 0;
			A2 = 0;
		end
	endcase
end



endmodule