sel_level.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

module sel_level(
		Memory_InData_A,		//DWT control Data_A
		Memory_OutData_A,		//DWT control OutData_A
		
		Memory_InData_B,		//DWT control Data_B
		Memory_OutData_B,		//DWT control OutData_B
		
		Sel_0,			       	//Select sel[3]
		Sel_1,			       	//Select EnableAvk
		Sel_2,			       	//Select EnableAcki
		
		DWT_InData,		//Out_Data_A
		DWT_OutData		//Out_OutData_A

		);


               
output	[19:0]	Memory_InData_A;		//DWT control Data_A
input	[19:0]	Memory_OutData_A;		//DWT control OutDat
                                                    
output	[19:0]	Memory_InData_B;		//DWT control Data_B
input	[19:0]	Memory_OutData_B;		//DWT control OutDat

input		    Sel_0;			       	//Select
input	[2:0]	Sel_1;			       	//Select
input	[2:0]	Sel_2;			       	//Select                                                    
                                        	            
output	[19:0]	DWT_InData;			//Out_Data_A                
input	[19:0]	DWT_OutData;		//Out_OutData_A

reg		[19:0]	Memory_InData_A;		//DWT control Data_A             
reg		[19:0]	Memory_InData_B;		//DWT control Data_B
reg		[19:0]	DWT_InData;			//Out_Data_A                

always @(Sel_0 or Sel_1 or Sel_2)
begin
	if(Sel_0) begin	//FDWT
		case(Sel_1)
//		3'b000:begin
//			DWT_InData = Memory_OutData_A;
//			Memory_InData_B  = DWT_OutData;
//		end
		3'b001:begin
			DWT_InData = Memory_OutData_A;
		    Memory_InData_B = DWT_OutData;
		end
		3'b010:begin
			DWT_InData = Memory_OutData_B;
			Memory_InData_A = DWT_OutData;
			end
			
		3'b011:begin
			DWT_InData = Memory_OutData_A;
			Memory_InData_B  = DWT_OutData;
		end
		3'b100:begin
			DWT_InData = Memory_OutData_B;
		    Memory_InData_A = DWT_OutData;
		end
		3'b101:begin
			DWT_InData = Memory_OutData_A;
			Memory_InData_B = DWT_OutData;
			end	
				
			
		default:begin                          
			DWT_InData = Memory_OutData_A; 
			Memory_InData_B  = DWT_OutData;
			end
		endcase
	end
	
	else begin  //IDWT
		case(Sel_2)
//		3'b000:begin
//			DWT_InData = Memory_OutData_A;
//			Memory_InData_B  = DWT_OutData;
//		end
		3'b001:begin
			DWT_InData = Memory_OutData_B;
	        Memory_InData_A = DWT_OutData;
		end
		3'b010:begin
			DWT_InData = Memory_OutData_A;
			Memory_InData_B = DWT_OutData;
		end
			
		3'b011:begin
			DWT_InData = Memory_OutData_B;
			Memory_InData_A  = DWT_OutData;
		end
		3'b100:begin
			DWT_InData = Memory_OutData_A;
		    	Memory_InData_B = DWT_OutData;
		end
		3'b101:begin
			DWT_InData = Memory_OutData_B;
			Memory_InData_A = DWT_OutData;
		end	                    
		default:begin
			DWT_InData = Memory_OutData_A;
			Memory_InData_B  = DWT_OutData;
		end
		endcase
	end
end

endmodule