fdwt97_top.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

//`timescale 1ns/10ps
`include "FDWT97_Control.v"
`include "FDWT97_Address_R.v"
`include "FDWT97_DataPath.v"
module FDWT97_TOP(
	Clk,
	Reset,
	indata,
	
	Write_En,
	Done,
	Address_OutR,
	Address_OutW,
	Choose_RW,
	Level_Choose,
	outdata
	);

parameter Data_Width = 20;
parameter Address_Width = 12;

input Clk;
input Reset;
input [Data_Width-1:0] indata;

output Write_En;
output Done;
output [Address_Width-1:0] Address_OutR;
output [Address_Width-1:0] Address_OutW;
output Choose_RW;
output [2:0] Level_Choose;
output [Data_Width-1:0] outdata;

wire DWT97_Reset;
wire Delay_Mode;
wire [4:0] Sel;

FDWT97_Control Control(
	.Clk(Clk),
	.Reset(DWT97_Reset),
	.Delay_Mode(Delay_Mode),
	
	.Sel(Sel)
	);
	
FDWT97_Address_R Address(
	.Clk(Clk),
	.Reset(Reset),
	
	.Address_OutR(Address_OutR),
	.Address_OutW(Address_OutW),
	.DWT97_Reset(DWT97_Reset),
	.Level_Choose(Level_Choose),
	.Delay_Mode(Delay_Mode),
	.Write_En(Write_En),
	.Choose_RW(Choose_RW),
	.Done(Done)
	);



FDWT97_DataPath DataPath(
	.Clk(Clk),
	.Reset(DWT97_Reset),
	.Sel(Sel),
	.indata(indata),
	
	
	.outdata(outdata)
	);




endmodule