chang3to2.v

来自「這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder」· Verilog 代码 · 共 40 行

module Chang3to2(
		In_Signal_A,		//DWT control We_A
		In_Signal_B,		//DWT control We_B
		Control_Signal,		//transform control We_A or We_B
		
		Sel,			//Select
		Out_Signal_A,		//Out_We_A
		Out_Signal_B		//Out_We_B
		);

input		In_Signal_A;
input		In_Signal_B;
input		Control_Signal;
               
input	[1:0]	Sel;
output		Out_Signal_A;
output		Out_Signal_B;

reg		Out_Signal_A;
reg		Out_Signal_B;

always @(Sel)
begin
	case(Sel)
	2'b00:begin
		Out_Signal_A = 0;
		Out_Signal_B = Control_Signal;
	end
	2'b01:begin
		Out_Signal_A = Control_Signal;
	        Out_Signal_B = 0;
	end
	default:begin
		Out_Signal_A = In_Signal_A;
		Out_Signal_B = In_Signal_B;
	end
	endcase
end

endmodule