fdwt_all.csf

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

DEFAULT_DEVICE_OPTIONS
{
	RESERVE_PIN = "AS INPUT TRI-STATED";
	RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
	HEXOUT_FILE_COUNT_DIRECTION = UP;
	HEXOUT_FILE_START_ADDRESS = 0;
	GENERATE_HEX_FILE = OFF;
	GENERATE_RBF_FILE = OFF;
	GENERATE_TTF_FILE = OFF;
	STRATIX_CRC_ERROR_CHECKING = OFF;
	RESERVE_RUNLU_AFTER_CONFIGURATION = OFF;
	RESERVE_DATA0_AFTER_CONFIGURATION = OFF;
	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
	DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE = OFF;
	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_CONFIGURATION_DEVICE = EPC2;
	FLEX10K_CONFIGURATION_DEVICE = EPC2;
	FLEX6K_CONFIGURATION_DEVICE = EPC1;
	MERCURY_CONFIGURATION_DEVICE = EPC2;
	EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
	APEX20K_CONFIGURATION_DEVICE = EPC2;
	USE_CONFIGURATION_DEVICE = ON;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	ENABLE_DEVICE_WIDE_OE = OFF;
	ENABLE_DEVICE_WIDE_RESET = OFF;
	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
	AUTO_RESTART_CONFIGURATION = OFF;
	ENABLE_VREFB_PIN = OFF;
	ENABLE_VREFA_PIN = OFF;
	SECURITY_BIT = OFF;
	USER_START_UP_CLOCK = OFF;
	APEX_II_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	STRATIX_UPDATE_MODE = STANDARD;
	USE_CHECKSUM_AS_USERCODE = OFF;
	MAX7000_JTAG_USER_CODE = FFFFFFFF;
	FLEX10K_JTAG_USER_CODE = 7F;
	MERCURY_JTAG_USER_CODE = FFFFFFFF;
	APEX20K_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_JTAG_USER_CODE = FFFFFFFF;
	RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
	ENABLE_JTAG_BST_SUPPORT = OFF;
}
AUTO_SLD_HUB_ENTITY
{
	AUTO_INSERT_SLD_HUB_ENTITY = ENABLE;
	HUB_INSTANCE_NAME = sld_hub_inst;
	HUB_ENTITY_NAME = sld_hub;
}
CHIP(FDWT_ALL)
{
	bidir[0] : IO_STANDARD = LVTTL;
	bidir[1] : IO_STANDARD = LVTTL;
	bidir[2] : IO_STANDARD = LVTTL;
	bidir[3] : IO_STANDARD = LVTTL;
	bidir[4] : IO_STANDARD = LVTTL;
	bidir[5] : IO_STANDARD = LVTTL;
	bidir[6] : IO_STANDARD = LVTTL;
	bidir[7] : IO_STANDARD = LVTTL;
	Clk : IO_STANDARD = LVTTL;
	Control_R_W : IO_STANDARD = LVTTL;
	FPGA_Check : IO_STANDARD = LVTTL;
	PC_Check_1 : IO_STANDARD = LVTTL;
	PC_Check_2 : IO_STANDARD = LVTTL;
	Reset : IO_STANDARD = LVTTL;
	s_done : IO_STANDARD = LVTTL;
	s_EnableAck[0] : IO_STANDARD = LVTTL;
	s_EnableAck[1] : IO_STANDARD = LVTTL;
	s_EnableAck[2] : IO_STANDARD = LVTTL;
	s_idone : IO_STANDARD = LVTTL;
	s_iEnableAck[0] : IO_STANDARD = LVTTL;
	s_iEnableAck[1] : IO_STANDARD = LVTTL;
	s_iEnableAck[2] : IO_STANDARD = LVTTL;
	s_rstdwt : IO_STANDARD = LVTTL;
	s_rstidwt : IO_STANDARD = LVTTL;
	Sel[0] : IO_STANDARD = LVTTL;
	Sel[1] : IO_STANDARD = LVTTL;
	Sel[2] : IO_STANDARD = LVTTL;
	bidir[0] : LOCATION = Pin_F32;
	bidir[1] : LOCATION = Pin_G32;
	bidir[2] : LOCATION = Pin_H32;
	bidir[3] : LOCATION = Pin_J32;
	bidir[4] : LOCATION = Pin_K32;
	bidir[5] : LOCATION = Pin_L32;
	bidir[6] : LOCATION = Pin_M32;
	bidir[7] : LOCATION = Pin_N32;
	Clk : LOCATION = Pin_W34;
	Control_R_W : LOCATION = Pin_G33;
	FPGA_Check : LOCATION = Pin_J31;
	PC_Check_1 : LOCATION = Pin_G31;
	PC_Check_2 : LOCATION = Pin_H31;
	Reset : LOCATION = Pin_F33;
	s_done : LOCATION = Pin_H30;
	s_EnableAck[0] : LOCATION = Pin_AK30;
	s_EnableAck[1] : LOCATION = Pin_AJ30;
	s_EnableAck[2] : LOCATION = Pin_AH30;
	s_idone : LOCATION = Pin_J30;
	s_iEnableAck[0] : LOCATION = Pin_AG30;
	s_iEnableAck[1] : LOCATION = Pin_AF30;
	s_iEnableAck[2] : LOCATION = Pin_AE30;
	s_rstdwt : LOCATION = Pin_L33;
	s_rstidwt : LOCATION = Pin_M33;
	Sel[0] : LOCATION = Pin_H33;
	Sel[1] : LOCATION = Pin_J33;
	Sel[2] : LOCATION = Pin_K33;
	RESERVE_ALL_UNUSED_PINS = "AS OUTPUT DRIVING GROUND";
	HEXOUT_FILE_COUNT_DIRECTION = UP;
	HEXOUT_FILE_START_ADDRESS = 0;
	GENERATE_HEX_FILE = OFF;
	GENERATE_RBF_FILE = OFF;
	GENERATE_TTF_FILE = OFF;
	STRATIX_CRC_ERROR_CHECKING = OFF;
	RESERVE_DATA0_AFTER_CONFIGURATION = OFF;
	RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION = OFF;
	RESERVE_RDYNBUSY_AFTER_CONFIGURATION = OFF;
	RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION = OFF;
	DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE = OFF;
	AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE = ON;
	EPROM_USE_CHECKSUM_AS_USERCODE = OFF;
	FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	MERCURY_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	APEX20K_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_CONFIG_DEVICE_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_CONFIGURATION_DEVICE = EPC2;
	FLEX10K_CONFIGURATION_DEVICE = EPC2;
	FLEX6K_CONFIGURATION_DEVICE = EPC1;
	MERCURY_CONFIGURATION_DEVICE = EPC2;
	EXCALIBUR_CONFIGURATION_DEVICE = EPC2;
	APEX20K_CONFIGURATION_DEVICE = EPC2;
	USE_CONFIGURATION_DEVICE = ON;
	ENABLE_INIT_DONE_OUTPUT = OFF;
	FLEX10K_ENABLE_LOCK_OUTPUT = OFF;
	ENABLE_DEVICE_WIDE_OE = OFF;
	ENABLE_DEVICE_WIDE_RESET = OFF;
	RELEASE_CLEARS_BEFORE_TRI_STATES = OFF;
	AUTO_RESTART_CONFIGURATION = OFF;
	ENABLE_VREFB_PIN = OFF;
	ENABLE_VREFA_PIN = OFF;
	SECURITY_BIT = OFF;
	USER_START_UP_CLOCK = OFF;
	APEX_II_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	FLEX10K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	FLEX6K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	MERCURY_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	EXCALIBUR_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	STRATIX_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	APEX20K_CONFIGURATION_SCHEME = "PASSIVE SERIAL";
	STRATIX_UPDATE_MODE = STANDARD;
	USE_CHECKSUM_AS_USERCODE = OFF;
	MAX7000_JTAG_USER_CODE = FFFFFFFF;
	FLEX10K_JTAG_USER_CODE = 7F;
	MERCURY_JTAG_USER_CODE = FFFFFFFF;
	APEX20K_JTAG_USER_CODE = FFFFFFFF;
	STRATIX_JTAG_USER_CODE = FFFFFFFF;
	RESERVE_NCEO_AFTER_CONFIGURATION = OFF;
	FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = ON;
	FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE = OFF;
	MAX7000_ENABLE_JTAG_BST_SUPPORT = ON;
	ENABLE_JTAG_BST_SUPPORT = OFF;
	DEVICE_FILTER_SPEED_GRADE = 1;
	DEVICE_FILTER_PIN_COUNT = 652;
	DEVICE_FILTER_PACKAGE = BGA;
	BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE = OFF;
	DEVICE = "EP20K400EBC652-1X";
}
COMPILER_SETTINGS
{
	RUN_TIMING_ANALYSES = ON;
	MERGE_HEX_FILE = OFF;
	FOCUS_ENTITY_NAME = |FDWT_ALL;
	FAMILY = APEX20KE;
	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
	DPRAM_32BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA1 = "MEGALAB COLUMN 1";
	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
	DPRAM_32BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "LOWER TO 1ESB UPPER TO 1";
	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_OUTPUT_EPXA1 = "MEGALAB COLUMN 1";
	DPRAM_DUAL_PORT_MODE_INPUT_EPXA1 = "DPRAM0 TO 1 DPRAM1 TO 2";
	DPRAM_32BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
	DPRAM_8BIT_16BIT_SINGLE_PORT_MODE_INPUT_EPXA1 = "MEGALAB COLUMN 1";
	DPRAM_DUAL_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
	DPRAM_SINGLE_PORT_MODE_OTHER_SIGNALS_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
	DPRAM_WIDE_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
	DPRAM_DEEP_MODE_OTHER_SIGNALS_EPXA4_10 = "MEGALAB COLUMN 3";
	DPRAM_DUAL_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
	DPRAM_SINGLE_PORT_MODE_OUTPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4ESB";
	DPRAM_WIDE_MODE_OUTPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4ESB";
	DPRAM_DEEP_MODE_OUTPUT_EPXA4_10 = "MEGALAB COLUMN 3";
	DPRAM_DUAL_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
	DPRAM_SINGLE_PORT_MODE_INPUT_EPXA4_10 = "DPRAM0 TO 3 DPRAM1 TO 4";
	DPRAM_WIDE_MODE_INPUT_EPXA4_10 = "LOWER TO 3 UPPER TO 4";
	DPRAM_DEEP_MODE_INPUT_EPXA4_10 = "MEGALAB COLUMN 3";
	DPRAM_OTHER_SIGNALS_EPXA4_10 = "DEFAULT OTHER ROUTING OPTIONS";
	DPRAM_OUTPUT_EPXA4_10 = "DEFAULT OUTPUT ROUTING OPTIONS";
	DPRAM_INPUT_EPXA4_10 = "DEFAULT INPUT ROUTING OPTIONS";
	STRIPE_TO_PLD_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
	PLD_TO_STRIPE_INTERRUPTS_EPXA4_10 = "MEGALAB COLUMN 2";
	PROCESSOR_DEBUG_EXTENSIONS_EPXA4_10 = "MEGALAB COLUMN 2";
	STRIPE_TO_PLD_BRIDGE_EPXA4_10 = "MEGALAB COLUMN 1";
	FAST_FIT_COMPILATION = OFF;
	SIGNAL_PROBE_AUTO_ASSIGN = 0;
	SIGNAL_PROBE_COMPILATION = OFF;
	SIGNAL_PROBE_ROUTING = ALL_SIGNAL_PROBE;
	LOGICLOCK_FITTER_TYPE = OFF;
	OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING = ON;
	OPTIMIZE_TIMING = NORMAL_COMPILATION;
	COMPILATION_LEVEL = FULL;
	SAVE_DISK_SPACE = ON;
	SPEED_DISK_USAGE_TRADEOFF = NORMAL;
	LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT = OFF;
}