fdwt_all.v

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

`include "PctoFPGA.v"
`include "FDWT97_TOP.v"
`include "IDWT97_TOP.v"
`include "sel_level.v"

module FDWT_ALL(
		Clk,			//Clock
		Reset,			//Reset State
		Control_R_W,		//Con_R_W = 1 ==> PC to FPGA,
					//Con_R_W = 0 ==> FPGA to PC.
		PC_Check_1,
		PC_Check_2,
		FPGA_Check,
		
		Sel,			//Sel[0] ==> 0 ==> Mamery Address(A,B) ==>Counter_Out
		    			//Sel[0] ==> 1 ==> Mamery Address(A,B) ==>DWT_Memory_(A,B)_Address
		    			//Sel[1] ==> 0 ==> bidirec(inp) <== Memory_Out_Data(A)
		    			//Sel[1] ==> 1 ==> bidirec(inp) <== Memory_Out_Data(B)
		    			//Sel[2]
		bidir,
		s_EnableAck,
		s_iEnableAck,
		s_rstdwt,
		s_rstidwt,
		s_done,
		s_idone

		);                                                                   

parameter Data_Width = 20;	//Data Width
parameter Address_Width = 12;	//Address Width 12bits = 4096
parameter OutData_Width = 8;	//Output Data Width

input	Clk;                 
input	Reset;
input	Control_R_W;
input	PC_Check_1;
input	PC_Check_2;

output 	FPGA_Check;

input	[2:0]	Sel;
                     
inout	[OutData_Width-1:0]	bidir;
		                                                                   
output	        s_done;
output	        s_idone;

wire	[Data_Width-1:0]	s_data_in;
output	[2:0]			s_EnableAck;
output	[2:0]			s_iEnableAck;

input				s_rstdwt;
input				s_rstidwt;

wire    [Data_Width-1:0]	s_OutData_Memory_A, s_OutData_Memory_B;
wire    [Data_Width-1:0]	s_InData_Memory_A, s_InData_Memory_B;
	
wire				s_FPGA_Check;
wire				Done_Counter_12bits;

wire	[Data_Width-1:0]	s_Fdata_out;
wire	[Data_Width-1:0]	s_Idata_out;





wire	[Data_Width-1:0]	s_Fdata_in     = Sel[2] ? s_data_in : 20'h00000;
wire	[Data_Width-1:0]	s_Idata_in     = Sel[2] ? 20'h00000 : s_data_in;

wire	[Address_Width-1:0]	FAddress_OutR;
wire	[Address_Width-1:0]	FAddress_OutW;
wire				FChoose_RW;
wire				FWrite_En;
wire	[Address_Width-1:0]	s_Faddress_a = FChoose_RW ? FAddress_OutW : FAddress_OutR;
wire	[Address_Width-1:0]	s_Faddress_b = FChoose_RW ? FAddress_OutR : FAddress_OutW;
wire				s_Flpm_a_rw  = FChoose_RW ? FWrite_En : 0;
wire				s_Flpm_b_rw  = FChoose_RW ? 0 : FWrite_En;

wire	[Address_Width-1:0]	IAddress_OutR;
wire	[Address_Width-1:0]	IAddress_OutW;
wire				IChoose_RW;
wire				IWrite_En;
wire	[Address_Width-1:0]	s_Iaddress_a = IChoose_RW ? IAddress_OutW : IAddress_OutR;
wire	[Address_Width-1:0]	s_Iaddress_b = IChoose_RW ? IAddress_OutR : IAddress_OutW;
wire				s_Ilpm_a_rw  = IChoose_RW ? IWrite_En : 0;
wire				s_Ilpm_b_rw  = IChoose_RW ? 0 : IWrite_En;

wire	[Data_Width-1:0]	Chang_Data_Out = Sel[2] ? s_Fdata_out  : s_Idata_out;
wire	[Address_Width-1:0]	s_address_a    = Sel[2]	? s_Faddress_a : s_Iaddress_a;
wire	[Address_Width-1:0]	s_address_b    = Sel[2]	? s_Faddress_b : s_Iaddress_b;
wire				s_lpm_a_rw     = Sel[2]	? s_Flpm_a_rw  : s_Ilpm_a_rw;
wire				s_lpm_b_rw     = Sel[2]	? s_Flpm_b_rw  : s_Ilpm_b_rw;

sel_level sel3(
		 .Memory_InData_A(s_InData_Memory_A),		//DWT control Data_A
		 .Memory_OutData_A(s_OutData_Memory_A),		//DWT control OutData_A
		
		 .Memory_InData_B(s_InData_Memory_B),		//DWT control Data_B
		 .Memory_OutData_B(s_OutData_Memory_B),		//DWT control OutData_B
		
		 .Sel_0(Sel[2]),		       	//Select
		 .Sel_1(s_EnableAck),		       	//Select
		 .Sel_2(s_iEnableAck),		       	//Select
		
		 .DWT_InData(s_data_in),		//Out_Data_A
		 .DWT_OutData(Chang_Data_Out)		//Out_OutData_A

		);

PcToFPGA PCFPGA(
		.Clk(Clk),			//Clock
		.Reset(Reset),			//Reset State
		.Control_R_W(Control_R_W),	//Con_R_W = 1 ==> PC to FPGA,
					        //Con_R_W = 0 ==> FPGA to PC.
		.PC_Check_1(PC_Check_1),
		.PC_Check_2(PC_Check_2),
		.FPGA_Check(FPGA_Check),
		
		.Sel({Sel[2],Sel[0],Sel[1],Sel[0]}),	        //Sel[0] ==> 0 ==> Mamery Address(A,B) ==>Counter_Out
		    			//Sel[0] ==> 1 ==> Mamery Address(A,B) ==>DWT_Memory_(A,B)_Address
		    			//Sel[1] ==> 0 ==> bidirec(inp) <== Memory_Out_Data(A)
		    			//Sel[1] ==> 1 ==> bidirec(inp) <== Memory_Out_Data(B)
		    			//Sel[2]

		.OutData_Memory_A(s_OutData_Memory_A),	//Memory_A_Data out
		.We_Memory_A(s_lpm_a_rw),
		.Address_Memory_A(s_address_a),
		.InData_Memory_A(s_InData_Memory_A),
		
		.OutData_Memory_B(s_OutData_Memory_B),	//Memory_A_Data out
		.We_Memory_B(s_lpm_b_rw),
		.Address_Memory_B(s_address_b),
		.InData_Memory_B(s_InData_Memory_B),
		
		.Done_Counter_128bits(Done_Counter_128bits),
		.bidir(bidir)
		);        

FDWT97_TOP FDWT(
	.Clk(Clk),
	.Reset(s_rstdwt),
	.indata(s_Fdata_in),
	
	.Write_En(FWrite_En),
	.Done(s_done),
	.Address_OutR(FAddress_OutR),
	.Address_OutW(FAddress_OutW),
	.Choose_RW(FChoose_RW),
	.Level_Choose(s_EnableAck),
	.outdata(s_Fdata_out)
	);
                
IDWT97_TOP IDWT(
	.Clk(Clk),
	.Reset(s_rstidwt),
	.indata(s_Idata_in),
	
	.Write_En(IWrite_En),
	.Done(s_idone),
	.Address_OutR(IAddress_OutR),
	.Address_OutW(IAddress_OutW),
	.Choose_RW(IChoose_RW),
	.Level_Choose(s_iEnableAck),
	.outdata(s_Idata_out)
	);


endmodule