fdwt_all.csf.rpt

這是一個二維的上提式9/7離散小波的Verilog的源碼,此為Encoder

FDWT_ALL - Quartus II Compilation Report File
-------------------------------------------------------------------------------

+---------------------------------------------------------------------------------------------+
|Report Information                                                                           |
+------------------+--------------------------------------------------------------------------+
|Project           |F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\db\FDWT_ALL.quartus_db|
|Compiler Settings |FDWT_ALL                                                                  |
|Quartus II Version|2.0 Build 188 01/22/2002                                                  |
+------------------+--------------------------------------------------------------------------+

Table of Contents
    Compilation Report
        Legal Notice
        Project Settings
            General Settings
        Results for "FDWT_ALL" Compiler Settings
            Summary
            Compiler Settings
            Messages
            Hierarchy
            Equations
            Device Options
            Floorplan View
            Pin-Out File
            Post-Synthesis Resource Utilization by Entity
            Resource Section
                Resource Usage Summary
                Input Pins
                Output Pins
                Bidir Pins
                All Package Pins
                Control Signals
                Global & Other Fast Signals
                Logical Memories
                Carry Chains
                Cascade Chains
                Embedded Cells
                Non-Global High Fan-Out Signals
                Peripheral Signals
                Local Routing Interconnect
                MegaLAB Interconnect
                LAB External Interconnect
                MegaLAB Usage Summary
                Row Interconnect
                LAB Column Interconnect
                ESB Column Interconnect
            Timing Analyses
                Timing Settings
                fmax (not incl. delays to/from pins)
                Register-to-Register fmax
                tpd (Pin to Pin Delays)
                tsu (Input Setup Times)
                th (Input Hold Times)
                tco (Clock to Output Delays)
            Processing Time

+-----------------------------------------------------------------------------+
|Legal Notice                                                                 |
+-----------------------------------------------------------------------------+
Copyright (C) 1991-2002 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.


+-----------------------------------------------------------------------------+
|General Settings                                                             |
+-----------------------------------------------------------------------------+
+-----------------+-------------------+
|Option           |Setting            |
+-----------------+-------------------+
|Start date & time|04/30/2004 14:18:36|
|Main task        |Compilation        |
|Settings name    |FDWT_ALL           |
+-----------------+-------------------+

+-----------------------------------------------------------------------------+
|Summary                                                                      |
+-----------------------------------------------------------------------------+
+-----------------------------------+-------------------------+
|Processing status                  |Fitting Successful       |
|Timing requirements/analysis status|No requirements          |
|Chip name                          |FDWT_ALL                 |
|Device name                        |EP20K400EBC652-1X        |
|Total logic elements               | 8778 / 16640 ( 52 % )   |
|Total pins                         | 27 / 493 ( 5 % )        |
|Total ESB bits                     | 163840 / 212992 ( 76 % )|
+-----------------------------------+-------------------------+

+-----------------------------------------------------------------------------+
|Compiler Settings                                                            |
+-----------------------------------------------------------------------------+
+------------------------------------------+------------------+
|Option                                    |Setting           |
+------------------------------------------+------------------+
|Chip name                                 |FDWT_ALL          |
|Family name                               |APEX20KE          |
|Focus entity name                         ||FDWT_ALL         |
|Device                                    |EP20K400EBC652-1X |
|Compilation mode                          |Full              |
|Disk space/compilation speed tradeoff     |Normal            |
|Preserve fewer node names                 |On                |
|Optimize timing                           |Normal Compilation|
|Optimize IOC register placement for timing|On                |
|Generate timing analyses                  |On                |
|Fast Fit compilation                      |Off               |
|SignalProbe compilation                   |Off               |
+------------------------------------------+------------------+

+-----------------------------------------------------------------------------+
|Messages                                                                     |
+-----------------------------------------------------------------------------+
Info: Found 0 design units and 0 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\FDWT_ALL.vwf
Warning: Parameter Declaration warning: ignored illegal part-select in parameter Declaration
Warning: Parameter Declaration warning: ignored illegal part-select in parameter Declaration
Info: Found 18 design units and 18 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\FDWT_ALL.v
  Info: Found entity 1: Counter_128bits
  Info: Found entity 2: memory
  Info: Found entity 3: bidirec
  Info: Found entity 4: Counter_State
  Info: Found entity 5: DataPath
  Info: Found entity 6: ControlPath
  Info: Found entity 7: Chang3to2
  Info: Found entity 8: PcToFPGA
  Info: Found entity 9: FDWT97_Control
  Info: Found entity 10: FDWT97_Address_R
  Info: Found entity 11: FDWT97_DataPath
  Info: Found entity 12: FDWT97_TOP
  Info: Found entity 13: IDWT97_Control
  Info: Found entity 14: IDWT97_Address_R
  Info: Found entity 15: IDWT97_DataPath
  Info: Found entity 16: IDWT97_TOP
  Info: Found entity 17: sel_level
  Info: Found entity 18: FDWT_ALL
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_ram_dq.tdf
  Info: Found entity 1: lpm_ram_dq
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\altram.tdf
  Info: Found entity 1: altram
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_mux.tdf
  Info: Found entity 1: lpm_mux
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\altshift.tdf
  Info: Found entity 1: altshift
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\muxlut.tdf
  Info: Found entity 1: muxlut
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_decode.tdf
  Info: Found entity 1: lpm_decode
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_counter.tdf
  Info: Found entity 1: lpm_counter
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\alt_synch_counter.tdf
  Info: Found entity 1: alt_synch_counter
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_add_sub.tdf
  Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\addcore.tdf
  Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\a_csnbuffer.tdf
  Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\Register_F.v
  Info: Found entity 1: Register_F
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\Add.v
  Info: Found entity 1: Add
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\lpm_compare.tdf
  Info: Found entity 1: lpm_compare
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\comptree.tdf
  Info: Found entity 1: comptree
Info: Found 1 design units and 1 entities in source file C:\quartus\libraries\megafunctions\cmpchain.tdf
  Info: Found entity 1: cmpchain
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\coff_a.v
  Info: Found entity 1: coff_a
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\coff_b.v
  Info: Found entity 1: coff_b
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\coff_r.v
  Info: Found entity 1: coff_r
Info: Found 1 design units and 1 entities in source file F:\Program_Back\Verilog\DWT\OK_PC\97_2D_1Level\FPGA\coff_l.v
  Info: Found entity 1: coff_l
Warning: Reduced register IDWT97_TOP:IDWT|IDWT97_Control:Control|CurrentState[2] with stuck data_in port to stuck value GND
Warning: Reduced register IDWT97_TOP:IDWT|IDWT97_Control:Control|CurrentState[3] with stuck data_in port to stuck value GND
Warning: Reduced register FDWT97_TOP:FDWT|FDWT97_Control:Control|CurrentState[2] with stuck data_in port to stuck value GND
Warning: Reduced register FDWT97_TOP:FDWT|FDWT97_Control:Control|CurrentState[3] with stuck data_in port to stuck value GND
Warning: Reduced register PcToFPGA:PCFPGA|ControlPath:A1|CurrentState[3] with stuck data_in port to stuck value GND
Warning: Reduced register PcToFPGA:PCFPGA|DataPath:B1|Counter_128bits:C1|Done with stuck data_in port to stuck value GND
Info: Ignored 988 buffer(s)
  Info: Ignored 988 SOFT buffer(s)
Info: Converted 12 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 8885 device resources
  Info: Implemented 10 input pins
  Info: Implemented 9 output pins
  Info: Implemented 8 bidirectional pins
  Info: Implemented 8778 logic cells
  Info: Implemented 80 RAM segments
Info: Selected device EP20K400EBC652-1X for design FDWT_ALL
Info: Started  fitting attempt 1 on Fri Apr 30 2004 at 14:23:20
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~56
  Info: Node sel_level:sel3|655~1410
  Info: Node sel_level:sel3|655~1419
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~42
  Info: Node sel_level:sel3|655~1144
  Info: Node sel_level:sel3|655~1153
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~43
  Info: Node sel_level:sel3|655~1163
  Info: Node sel_level:sel3|655~1172
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~44
  Info: Node sel_level:sel3|655~1182
  Info: Node sel_level:sel3|655~1191
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~45
  Info: Node sel_level:sel3|655~1201
  Info: Node sel_level:sel3|655~1210
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~46
  Info: Node sel_level:sel3|655~1220
  Info: Node sel_level:sel3|655~1229
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~47
  Info: Node sel_level:sel3|655~1239
  Info: Node sel_level:sel3|655~1248
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~48
  Info: Node sel_level:sel3|655~1258
  Info: Node sel_level:sel3|655~1267
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~49
  Info: Node sel_level:sel3|655~1277
  Info: Node sel_level:sel3|655~1286
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~50
  Info: Node sel_level:sel3|655~1296
  Info: Node sel_level:sel3|655~1305
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~51
  Info: Node sel_level:sel3|655~1315
  Info: Node sel_level:sel3|655~1324
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~52
  Info: Node sel_level:sel3|655~1334
  Info: Node sel_level:sel3|655~1343
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~53
  Info: Node sel_level:sel3|655~1353
  Info: Node sel_level:sel3|655~1362
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~54
  Info: Node sel_level:sel3|655~1372
  Info: Node sel_level:sel3|655~1381
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~55
  Info: Node sel_level:sel3|655~1391
  Info: Node sel_level:sel3|655~1400
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~57
  Info: Node sel_level:sel3|655~1429
  Info: Node sel_level:sel3|655~1438
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~40
  Info: Node sel_level:sel3|655~1106
  Info: Node sel_level:sel3|655~1115
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~41
  Info: Node sel_level:sel3|655~1125
  Info: Node sel_level:sel3|655~1134
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~58
  Info: Node sel_level:sel3|655~1448
  Info: Node sel_level:sel3|655~1457
Info: Found combinatorial loop of 3 nodes
  Info: Node sel_level:sel3|655~59
  Info: Node sel_level:sel3|655~1467
  Info: Node sel_level:sel3|655~1476
Warning: Found pins functioning as undefined clocks and/or memory enables
  Info: Assuming node Clk is an undefined clock
Info: Clock Clk has Internal fmax of 21.14 MHz between source register FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Register_F:P4|Reg_R[0] and destination register FDWT97_TOP:FDWT|FDWT97_DataPath:DataPath|Register_F:P5|Reg_R[6] (period= 47.296 ns)
  Info: + Longest register to register delay is 46.872 ns