dispdecoder.fit.summary

来自「采用Verilog HDL语言编写的数字频率计」· SUMMARY 代码 · 共 11 行

Flow Status : Successful - Mon Jul 17 22:27:25 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : dispdecoder
Top-level Entity Name : dispdecoder
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 10 / 64 ( 15 % )
Total pins : 47 / 68 ( 69 % )
Device : EPM7064STC100-5
Timing Models : Final