data_mux.fit.summary

采用Verilog HDL语言编写的数字频率计

Flow Status : Successful - Mon Jul 17 22:48:42 2006
Quartus II Version : 4.2 Build 157 12/07/2004 SJ Full Version
Revision Name : data_mux
Top-level Entity Name : data_mux
Family : MAX7000S
Met timing requirements : N/A
Total macrocells : 8 / 32 ( 25 % )
Total pins : 35 / 36 ( 97 % )
Device : EPM7032SLC44-5
Timing Models : Final