main.tan.qmsg

来自「采用Verilog HDL语言编写的数字频率计」· QMSG 代码 · 共 21 行 · 第 1/5 页

{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[4\]~146 " "Info: Node \"dispdecoder:inst5\|data_out\[4\]~146\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "dispdecoder:inst5\|data_out\[5\]~142 " "Info: Node \"dispdecoder:inst5\|data_out\[5\]~142\"" {  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}  } { { "dispdecoder.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/dispdecoder.v" 9 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|fref~126 " "Info: Node \"gate_control:inst3\|fref~126\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 36 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s100hz~25 " "Info: Node \"gate_control:inst3\|dp_s100hz~25\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}
{ "Info" "ITAN_SCC_LOOP" "1 " "Info: Found combinational loop of 1 nodes" { { "Info" "ITAN_SCC_NODE" "gate_control:inst3\|dp_s1hz~24 " "Info: Node \"gate_control:inst3\|dp_s1hz~24\"" {  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}  } { { "gate_control.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/cymometer/main/gate_control.v" 12 -1 0 } }  } 0}