the_6th_pc.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 31 行

//*****************************************************************************************************
// ** Version      :1.11
// ** File name    :The_6th_pc.v
// ** Module name  :The_6th_PC
// ****************************************************************************************************
 module The_6th_PC(pc_out, pc_in, clk, reset, load_enable,count_enable);
 	parameter width = 8;
 	
 	output[width-1:0]		 pc_out;             //data output;
 	
 	input [width-1:0]   pc_in;              //data input;
 	input clk;
 	input reset;
 	input load_enable, count_enable; 
 	
 	reg [width-1:0] pc_out;
 	
 	always @(posedge clk or negedge reset)
 	   begin
 		if (!reset)
 		   pc_out = 8'b0;
 		else if (load_enable)           // if load enable
 		   pc_out = pc_in;
 		else if (count_enable)          // if count enable
 		   pc_out = pc_out + 1;
 		else
 		   pc_out = pc_out;
 		
 	   end
 endmodule