the_6th_mem.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 35 行

// **********************************************************
// **Revision     : 1.11
// **File name    : The_6th_mem.v
// **Module name  : The_6th_mem
// **********************************************************

module The_6th_mem(mem_data,mem_address,FPGACS,FPGAWR,FPGARD);
   
   inout [7:0] mem_data;
   input [7:0] mem_address;
   input FPGACS,FPGAWR,FPGARD;
   
   wire   [7:0] mem_in;
             
   reg   [7:0] mem_out;
   reg   [7:0] mem[255:0];

   assign mem_in = mem_data;
   assign mem_data = (~FPGACS && ~FPGARD) ? mem_out : 'bz;
   
   always @(mem_in or mem_address or FPGACS or FPGAWR or FPGARD)
      begin
	if(!FPGACS)
	begin
	   if(!FPGAWR)
	   begin
	        mem[mem_address] = mem_in;
           	 	 mem_out = mem[mem_address];
           end        
	   else
	   if(!FPGARD)
           	mem_out = mem[mem_address];
        end
      end
 endmodule