the_6th_register.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 31 行

//*****************************************************************************************************
// * Version    : 1.0
// * File name  : The_6th_register.v
// * Module name: The_6th_register
// *****************************************************************************************************/
 module The_6th_register(register_out, register_in, clk, reset, load_enable);
 	 
	 
	 parameter w=8;	
 	output [w-1:0]	 register_out;
 	input  [w-1:0]  register_in;
 	input  clk;
 	input  reset;
 	input  load_enable;
 	
 	reg [w-1:0] register_out;
 	
 	always @(posedge clk or negedge reset)
 	   begin
 		if (!reset)
 		   register_out = 8'b0;
 		else if (load_enable)
 		   register_out = register_in;
 		else
 		   register_out = register_out;
 		
 	   end
 endmodule