the_6th_mux2.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 15 行

//******************************************************************************************
//**Version       : 1.11
//**File Name     : The_6th_mux2.v
//**Module Name   : The_6th_mux2
//*******************************************************************************************
module The_6th_mux2_1 (mux2_out, m0_in, m1_in, sel_in);
   
   output [7:0] mux2_out;   
   input  [7:0] m0_in, m1_in;
   input   sel_in;
   
   assign mux2_out = sel_in ? m1_in : m0_in;
   
endmodule