the_6th_mul.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 44 行

module The_6th_MUL(OUT_HIGH,OUT_LOW,IN_1,IN_2);
    parameter width = 8;
    output [width-1:0] OUT_HIGH;         reg  [width-1:0] OUT_HIGH;    	//结果的高八位
    output [width-1:0] OUT_LOW;          reg  [width-1:0] OUT_LOW;      //结果的低八位
    input  [width-1:0] IN_1;                               		//被乘数
    input  [width-1:0] IN_2;                               		//乘数
    
    reg  [width-1:0] HIGH;
    reg  [width-1:0] LOW;
    
    always @(HIGH or LOW )
    begin
        {OUT_HIGH,OUT_LOW} = {HIGH,LOW};
    end
    
    always @(IN_1 or IN_2)
    begin								//计算IN_1乘以IN_2
        {HIGH,LOW} = 'b0;
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[7]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[6]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[5]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[4]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[3]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[2]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[1]}}};
        
        {HIGH,LOW} ={HIGH[width-2:0],LOW[width-1:0],HIGH[width-1]};
        {HIGH,LOW} ={HIGH,LOW} + {8'b0,IN_1&{8{IN_2[0]}}};
        
    end
endmodule