the_6th_div.v

来自「一个自己写的8位CPU程序」· Verilog 代码 · 共 29 行

module The_6th_DIV (quo,rem,a,b);
    parameter size = 8;
    input [size-1:0] a,b;
    output [size-1:0] quo,rem;
    reg [size-1:0] quo,rem;
    reg [2:0] i;  
    reg [7:0] temp;  
    always @(a or b)
    begin
       i=7;
       temp=a;
       quo=0;rem=0;
       repeat(8)
       begin
           {rem}={rem[6:0],temp[7]};
           temp=temp<<1;           
           if (rem>=b) 
           begin
               rem=rem-b;
               quo[i]=1;
           end
           else
           begin
              quo[i]=0;
           end
           i=i-1;
       end
   end
endmodule