testbench2.v

一个自己写的8位CPU程序

//***************************************************
// Version		: 1.11                                        
// Module Name 	: test_all                                     
// Author		: team32                                    
//***************************************************

`timescale 1ns/1ns

module test_all;
	wire [7:0] data_bus;
	wire [7:0] add_bus;
	wire cs_wire;
	wire wr_wire;
	wire rd_wire;
	
	reg clk_wire;
	reg reset_wire;

	The_6th_CPU b(.data(data_bus),.address_out(add_bus),.CS(cs_wire),.WR(wr_wire),.RD(rd_wire),.clk(clk_wire),.reset(reset_wire));
	The_6th_mem m(.mem_data(data_bus),.mem_address(add_bus),.FPGACS(cs_wire),.FPGAWR(wr_wire),.FPGARD(rd_wire));

	initial
	begin
		  $monitor($time,,,"AC=%b,AR=%d,AB_sel=%b,IR=%d,PC=%d,state=%d,mux_DB_sel=%b,mem[%d]=%d,GR[%d]=%b,ALU=%h,GR_address=%d,GR_out=%b,GR[1]=%h,GR[0]=%h,c=%b,Z=%b,quo_out=%b,rem_out=%b",
                b.ac.register_out,b.ar.register_out,b.mux_AB_sel,b.ir.register_out,b.PC.pc_out,b.CU.state,b.mux_DB_sel,b.ar.register_out,m.mem[b.ar.register_out],b.ir.register_out[2:0],b.GR.GR_out,b.ALU.ALU_O,b.GR.GR_address,b.GR.GR_out,b.GR.register[1],b.GR.register[0],b.c_reg.register_out,b.z_reg.register_out,b.quo_out,b.rem_out);             
				
		clk_wire=1'b0;
		reset_wire=1'b1;
		
                m.mem[0]='b00000001;
                m.mem[1]='b00010100;
                m.mem[2]='b00010000;
                m.mem[3]='b00010101;
                m.mem[4]='b11110000;
                m.mem[5]='b00001000;
                m.mem[6]='b00010110;
                m.mem[7]='b00011000;
                m.mem[8]='b00010111;
                m.mem[9]='b11111000;
                m.mem[20]='b00010000;
                m.mem[21]='b00010000;
		
		
		#5 reset_wire='b0;
		#4 reset_wire='b1;
		//#80 $display("************************************");
		#1000 $stop;
		
	end
	
	always #2 clk_wire=~clk_wire;
	
	

endmodule