the_6th_cpu.v

一个自己写的8位CPU程序

// ******************************************************************
// **Revision     : 1.11
// **Module name  : The_6th_CPU.v
// **Author       :
// ******************************************************************
module The_6th_CPU(data,address_out,CS,WR,RD,clk,reset);      //???
	inout [7:0]data;                    //
	input clk;                          //????
	input reset;                        //????
	
   output [7:0]address_out;            //????
	output CS,WR,RD;                    //?/????
	
	wire [7:0] data_bus;                //????
   wire [7:0] alu_out;                 //?ALU????????
   wire [7:0] gr_out;                  //????????????
   wire [7:0] ar_out;                  //????????????
   wire [7:0] ir_out;                  //????????????
   wire [7:0] ac_out;                  //??????????
   wire [7:0] pc_out;                  //
   wire [7:0] data_out;                //??????
   wire [7:0] data_in;                 //??????
   wire c_out;                         //C???????
   wire z_out;                         //Z???????
   wire is_zero;                       //??????(Z???????)
   wire [7:0] OUT_HIGH;                //???????
	wire [7:0] OUT_LOW;                 //???????
   wire [7:0] quo_out;                 //???
   wire [7:0] rem_out;                 //????
	
   wire [2:0] gr_address;              //?????????
    	
  	wire [4:0] alu_op;                  //ALU????
   wire [2:0] mux_DB_sel;              //??????????
   wire mux_AB_sel;                    //??????????
   wire RD_sel;                        //????
   wire WR_sel;                        //????
   wire cs_sel;                        //
   
   wire CLE;                           //C???????
   wire ZLE;                           //Z???????
   wire IRLE;                          //???????
   wire ARLE;                          //???????
   wire ACLE;                          //?????
   wire GRLE;                          //????????
   wire PCLE;                          //?????????
   wire PCCE;                          //?????????
   wire alu_c;                         //?ALU?????????????
    	
   assign CS=cs_sel;                   //
   assign WR=WR_sel;                   //
   assign RD=RD_sel;                   //
   	
    	
   assign is_zero=(alu_out=='b0)?'b1:'b0;      //?"0"??
   
   assign data_in=data;                   //
   assign data_out=data_bus;              //???????
   assign data=(~CS&&~WR)?data_out:8'bz;        //
   	
   The_6th_register #(1) c_reg(.register_out(c_out),.register_in(alu_c),.clk(clk),.reset(reset),.load_enable(CLE));
                                                                               //??C?????(????)
   
   The_6th_register #(1) z_reg(.register_out(z_out),.register_in(is_zero),.clk(clk),.reset(reset),.load_enable(ZLE));
                                                                               //??Z?????
   
   The_6th_register ir(.register_out(ir_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(IRLE));
                                                                               //???????
   
   The_6th_register ar(.register_out(ar_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(ARLE));
                                                                               //???????
   
   The_6th_register ac(.register_out(ac_out),.register_in(data_bus),.clk(clk),.reset(reset),.load_enable(ACLE));
                                                                               //?????
   
   The_6th_mux8_1 mux_db (.mux8_out(data_bus),.m0_in(ac_out),.m1_in(alu_out),.m2_in(data_in),.m3_in(OUT_HIGH),
                  .m4_in (OUT_LOW),.m5_in(gr_out),.m6_in(quo_out),.m7_in(rem_out),.sel_in(mux_DB_sel));
                                                                               //??"8?1"??
   
   The_6th_mux2_1 mux_ab(.mux2_out(address_out),.m0_in(pc_out),.m1_in(ar_out),.sel_in(mux_AB_sel));
                                                                               //??"2?1"??
   
   The_6th_GR GR(.GR_out(gr_out),.GR_in(data_bus),.clk(clk),.reset(reset),.GR_address(gr_address),.load_enable(GRLE));
                                                                               //????????
   
   The_6th_ALU ALU(.ALU_O(alu_out),.ALU_C(alu_c),.C_in(c_out),.op(alu_op),.AC_in(ac_out),.GR_in(gr_out));
                                                                               //??ALU
   
   The_6th_MUL MUL (.OUT_HIGH(OUT_HIGH),.OUT_LOW(OUT_LOW),.IN_1(ac_out),.IN_2(gr_out));         //?????
   
   The_6th_DIV DIV (.quo(quo_out),.rem(rem_out),.a(ac_out),.b(gr_out));                //?????
   
   The_6th_PC PC(.pc_out(pc_out),.pc_in(data_bus),.clk(clk),.reset(reset),.load_enable(PCLE),.count_enable(PCCE));
                                                                               //???????
   
   The_6th_CU CU(.CLE(CLE),.ZLE(ZLE),.ALU_OP(alu_op),.ACLE(ACLE),.GR_address(gr_address),.GRLE(GRLE),.IRLE(IRLE),.ARLE(ARLE),.PCLE(PCLE),.PCCE(PCCE),.mux_DB_sel(mux_DB_sel),.mux_AB_sel(mux_AB_sel),.CS(cs_sel),.RD(RD_sel),.WR(WR_sel),.clk(clk),.reset(reset),.C_in(c_out),.Z_in(z_out),.IR_in(ir_out),.MUL_enable(MUL_enable),.DIV_enable(DIV_enable));
                                                                               //?????
endmodule