add16_adv.mpf

在ISE下用verilog开发的16位进位现行加法器

; Default is on
VoptFlow = 1

; vopt automatic SDF
; If automatic design optimization is on, enables automatic compilation
; of SDF files.
; Default is on, uncomment to turn off.
; VoptAutoSDFCompile = 0

; Simulator resolution
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
resolution = 10ps

; User time unit for run commands
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
; unit specified for Resolution. For example, if Resolution is 100ps,
; then UserTimeUnit defaults to ps.
; Should generally be set to default.
UserTimeUnit = default

; Default run length
RunLength = 100 ps

; Maximum iterations that can be run without advancing simulation time
IterationLimit = 5000

; Control PSL and Verilog Assume directives during simulation
; Set SimulateAssumeDirectives = 0 to disable assume being simulated as asserts
; Set SimulateAssumeDirectives = 1 to enable assume simulation as asserts
; SimulateAssumeDirectives = 1 

; Control the simulation of PSL and SVA
; These switches can be overridden by the vsim command line switches:
;    -psl, -nopsl, -sva, -nosva.
; Set SimulatePSL = 0 to disable PSL simulation
; Set SimulatePSL = 1 to enable PSL simulation (default)
; SimulatePSL = 1 
; Set SimulateSVA = 0 to disable SVA simulation
; Set SimulateSVA = 1 to enable concurrent SVA simulation (default)
; SimulateSVA = 1 

; Directives to license manager can be set either as single value or as
; space separated multi-values:
; vhdl          Immediately reserve a VHDL license
; vlog          Immediately reserve a Verilog license
; plus          Immediately reserve a VHDL and Verilog license
; nomgc         Do not look for Mentor Graphics Licenses
; nomti         Do not look for Model Technology Licenses
; noqueue       Do not wait in the license queue when a license is not available
; viewsim       Try for viewer license but accept simulator license(s) instead
;               of queuing for viewer license (PE ONLY)
; noviewer	Disable checkout of msimviewer and vsim-viewer license 
;		features (PE ONLY)
; noslvhdl	Disable checkout of qhsimvh and vsim license features
; noslvlog	Disable checkout of qhsimvl and vsimvlog license features
; nomix		Disable checkout of msimhdlmix and hdlmix license features
; nolnl		Disable checkout of msimhdlsim and hdlsim license features
; mixedonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog license 
;		features
; lnlonly	Disable checkout of qhsimvh,qhsimvl,vsim,vsimvlog,msimhdlmix,
;		hdlmix license features
; Single value:
; License = plus
; Multi-value:
; License = noqueue plus

; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
BreakOnAssertion = 3

; VHDL assertion Message Format
; %S - Severity Level 
; %R - Report Message
; %T - Time of assertion
; %D - Delta
; %I - Instance or Region pathname (if available)
; %i - Instance pathname with process
; %O - Process name
; %K - Kind of object path is to return: Instance, Signal, Process or Unknown
; %P - Instance or Region path without leaf process
; %F - File
; %L - Line number of assertion or, if assertion is in a subprogram, line
;      from which the call is made
; %% - Print '%' character
; If specific format for assertion level is defined, use its format.
; If specific format is not defined for assertion level:
; - and if failure occurs during elaboration, use AssertionFormatBreakLine;
; - and if assertion triggers a breakpoint (controlled by BreakOnAssertion
;   level), use AssertionFormatBreak;
; - otherwise, use AssertionFormat.
; AssertionFormatBreakLine = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F Line: %L\n"
; AssertionFormatBreak     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormat          = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatNote      = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatWarning   = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
; AssertionFormatError     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormatFail      = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"
; AssertionFormatFatal     = "** %S: %R\n   Time: %T  Iteration: %D  %K: %i File: %F\n"

; Assertion File - alternate file for storing VHDL/PSL/Verilog assertion messages
; AssertFile = assert.log


; Simulation Breakpoint messages
; This flag controls the display of function names when reporting the location
; where the simulator stops do to a breakpoint or fatal error.
; Example w/function name:  # Break in Process ctr at counter.vhd line 44
; Example wo/function name: # Break at counter.vhd line 44
ShowFunctions = 1


; Default radix for all windows and commands.
; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
DefaultRadix = symbolic

; VSIM Startup command
; Startup = do startup.do

; File for saving command transcript
TranscriptFile = transcript

; File for saving command history
; CommandHistory = cmdhist.log

; Specify whether paths in simulator commands should be described
; in VHDL or Verilog format.
; For VHDL, PathSeparator = /
; For Verilog, PathSeparator = .
; Must not be the same character as DatasetSeparator.
PathSeparator = /

; Specify the dataset separator for fully rooted contexts.
; The default is ':'. For example: sim:/top
; Must not be the same character as PathSeparator.
DatasetSeparator = :

; Specify a unique path separator for the Signal Spy set of functions. 
; The default will be to use the PathSeparator variable.
; Must not be the same character as DatasetSeparator.
; SignalSpyPathSeparator = /

; Disable VHDL assertion messages
; IgnoreNote = 1
; IgnoreWarning = 1
; IgnoreError = 1
; IgnoreFailure = 1

; Disable System Verilog assertion messages
; Info and Warning are disabled by default
; IgnoreSVAInfo = 0
; IgnoreSVAWarning = 0
; IgnoreSVAError = 1
; IgnoreSVAFatal = 1

; Default force kind. May be freeze, drive, deposit, or default
; or in other terms, fixed, wired, or charged.
; A value of "default" will use the signal kind to determine the
; force kind, drive for resolved signals, freeze for unresolved signals
; DefaultForceKind = freeze

; If zero, open files when elaborated; otherwise, open files on
; first read or write.  Default is 0.
; DelayFileOpen = 1

; Control VHDL files opened for write.
;   0 = Buffered, 1 = Unbuffered
UnbufferedOutput = 0

; Control the number of VHDL files open concurrently.
; This number should always be less than the current ulimit
; setting for max file descriptors.
;   0 = unlimited
ConcurrentFileLimit = 40

; Control the number of hierarchical regions displayed as
; part of a signal name shown in the Wave window.
; A value of zero tells VSIM to display the full name.
; The default is 0.
; WaveSignalNameWidth = 0

; Turn off warnings when changing VHDL constants and generics
; Default is 1 to generate warning messages
; WarnConstantChange = 0

; Turn off warnings from the std_logic_arith, std_logic_unsigned
; and std_logic_signed packages.
; StdArithNoWarnings = 1

; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
; NumericStdNoWarnings = 1

; Control the format of the (VHDL) FOR generate statement label
; for each iteration.  Do not quote it.
; The format string here must contain the conversion codes %s and %d,
; in that order, and no other conversion codes.  The %s represents
; the generate_label; the %d represents the generate parameter value
; at a particular generate iteration (this is the position number if
; the generate parameter is of an enumeration type).  Embedded whitespace
; is allowed (but discouraged); leading and trailing whitespace is ignored.
; Application of the format must result in a unique scope name over all
; such names in the design so that name lookup can function properly.
; GenerateFormat = %s__%d

; Specify whether checkpoint files should be compressed.
; The default is 1 (compressed).
; CheckpointCompressMode = 0

; Specify whether to enable SystemVerilog DPI out-of-the-blue call. 
; Out-of-the-blue call refers to a SystemVerilog export function call 
; directly from a C function that don't have the proper context setup 
; as done in DPI-C import C functions. When this is enabled, one can 
; call a DPI export function (but not task) from any C code.
; The default is 0 (disabled).
; DpiOutOfTheBlue = 1

; List of dynamically loaded objects for Verilog PLI applications
; Veriuser = veriuser.sl

; Specify default options for the restart command. Options can be one
; or more of: -force -nobreakpoint -nolist -nolog -nowave -noassertions
; DefaultRestartOptions = -force

; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
; (> 500 megabyte memory footprint). Default is disabled.
; Specify number of megabytes to lock.
; LockedMemory = 1000

; HP-UX 11.00 ONLY - Use /usr/lib/libCsup_v2.sl for shared object loading.
; This is necessary when C++ files have been compiled with aCC's -AA option.
; The default behavior is to use /usr/lib/libCsup.sl.
; UseCsupV2 = 1

; Turn on (1) or off (0) WLF file compression.
; The default is 1 (compress WLF file).
; WLFCompress = 0

; Specify whether to save all design hierarchy (1) in the WLF file
; or only regions containing logged signals (0).
; The default is 0 (save only regions with logged signals).
; WLFSaveAllRegions = 1

; WLF file time limit.  Limit WLF file by time, as closely as possible,
; to the specified amount of simulation time.  When the limit is exceeded
; the earliest times get truncated from the file.
; If both time and size limits are specified the most restrictive is used.
; UserTimeUnits are used if time units are not specified.
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
; WLFTimeLimit = 0

; WLF file size limit.  Limit WLF file size, as closely as possible,
; to the specified number of megabytes.  If both time and size limits
; are specified then the most restrictive is used.
; The default is 0 (no limit).
; WLFSizeLimit = 1000

; Specify whether or not a WLF file should be deleted when the
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
; The default is 0 (do not delete WLF file when simulation ends).
; WLFDeleteOnQuit = 1

; Specify whether or not a WLF file should be optimized during 
; simulation.  If set to 0, the WLF file will not be optimized.
; The default is 1, optimize the WLF file.
; WLFOptimize = 0

; Specify the name of the WLF file.
; The default is vsim.wlf
; WLFFilename = vsim.wlf

; WLF reader cache size limit.  Specifies the internal WLF file cache size,