prev_cmp_dianzirili.qmsg

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dianzirili.v(121) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(121): truncated value with size 2 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 121 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dianzirili.v(122) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(122): truncated value with size 2 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 122 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 dianzirili.v(123) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(123): truncated value with size 2 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 123 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(137) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(137): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 137 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(138) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(138): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 138 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(151) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(151): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 151 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(152) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(152): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 152 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(165) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(165): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 165 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(166) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(166): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 166 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(180) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(180): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 180 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(181) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(181): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 181 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(188) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(188): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 188 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(189) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(189): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 189 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(196) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(196): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 196 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(197) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(197): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 197 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(212) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(212): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 212 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(213) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(213): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 213 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dianzirili.v(226) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(226): truncated value with size 32 to match size of target (3)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 226 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 dianzirili.v(236) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(236): truncated value with size 32 to match size of target (4)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 236 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "dianzirili.v(240) " "Warning (10270): Verilog HDL Case Statement warning at dianzirili.v(240): incomplete case statement has no default case item" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "hour dianzirili.v(240) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable \"hour\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "min dianzirili.v(240) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable \"min\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "sec dianzirili.v(240) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable \"sec\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "week dianzirili.v(240) " "Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable \"week\", which holds its previous value in one or more paths through the always construct" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 dianzirili.v(251) " "Warning (10230): Verilog HDL assignment warning at dianzirili.v(251): truncated value with size 32 to match size of target (1)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 251 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "" 0}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "alert1 0 dianzirili.v(39) " "Warning (10030): Net \"alert1\" at dianzirili.v(39) has no driver or initial value, using a default initial value '0'" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 39 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "week\[0\] dianzirili.v(240) " "Info (10041): Inferred latch for \"week\[0\]\" at dianzirili.v(240)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "week\[1\] dianzirili.v(240) " "Info (10041): Inferred latch for \"week\[1\]\" at dianzirili.v(240)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "week\[2\] dianzirili.v(240) " "Info (10041): Inferred latch for \"week\[2\]\" at dianzirili.v(240)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "week\[3\] dianzirili.v(240) " "Info (10041): Inferred latch for \"week\[3\]\" at dianzirili.v(240)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "sec\[0\] dianzirili.v(240) " "Info (10041): Inferred latch for \"sec\[0\]\" at dianzirili.v(240)" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}