dianzirili.tan.qmsg

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 201 " "Warning: Circuit may not operate. Detected 201 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "mon1\[2\] mon1\[3\] clk 5.001 ns " "Info: Found hold time violation between source  pin or register \"mon1\[2\]\" and destination pin or register \"mon1\[3\]\" for clock \"clk\" (Hold time is 5.001 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "5.372 ns + Largest " "Info: + Largest clock skew is 5.372 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 16.029 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 16.029 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 12 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 12; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.712 ns) 2.861 ns sound\[0\] 2 REG LCFF_X15_Y8_N9 4 " "Info: 2: + IC(1.295 ns) + CELL(0.712 ns) = 2.861 ns; Loc. = LCFF_X15_Y8_N9; Fanout = 4; REG Node = 'sound\[0\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { clk sound[0] } "NO