📄 dianzirili.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register sec1\[5\] register minclk 88.48 MHz 11.302 ns Internal " "Info: Clock \"clk\" has Internal fmax of 88.48 MHz between source register \"sec1\[5\]\" and destination register \"minclk\" (period= 11.302 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.856 ns + Longest register register " "Info: + Longest register to register delay is 1.856 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sec1\[5\] 1 REG LCFF_X13_Y9_N19 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X13_Y9_N19; Fanout = 5; REG Node = 'sec1\[5\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { sec1[5] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.819 ns) + CELL(0.346 ns) 1.165 ns WideNor5~25 2 COMB LCCOMB_X14_Y6_N10 2 " "Info: 2: + IC(0.819 ns) + CELL(0.346 ns) = 1.165 ns; Loc. = LCCOMB_X14_Y6_N10; Fanout = 2; COMB Node = 'WideNor5~25'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.165 ns" { sec1[5] WideNor5~25 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 130 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.209 ns) + CELL(0.053 ns) 1.427 ns WideNor5 3 COMB LCCOMB_X14_Y6_N0 2 " "Info: 3: + IC(0.209 ns) + CELL(0.053 ns) = 1.427 ns; Loc. = LCCOMB_X14_Y6_N0; Fanout = 2; COMB Node = 'WideNor5'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.262 ns" { WideNor5~25 WideNor5 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 130 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.221 ns) + CELL(0.053 ns) 1.701 ns minclk~133 4 COMB LCCOMB_X14_Y6_N28 1 " "Info: 4: + IC(0.221 ns) + CELL(0.053 ns) = 1.701 ns; Loc. = LCCOMB_X14_Y6_N28; Fanout = 1; COMB Node = 'minclk~133'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.274 ns" { WideNor5 minclk~133 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.856 ns minclk 5 REG LCFF_X14_Y6_N29 2 " "Info: 5: + IC(0.000 ns) + CELL(0.155 ns) = 1.856 ns; Loc. = LCFF_X14_Y6_N29; Fanout = 2; REG Node = 'minclk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { minclk~133 minclk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 32.70 % ) " "Info: Total cell delay = 0.607 ns ( 32.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.249 ns ( 67.30 % ) " "Info: Total interconnect delay = 1.249 ns ( 67.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.856 ns" { sec1[5] WideNor5~25 WideNor5 minclk~133 minclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.856 ns" { sec1[5] WideNor5~25 WideNor5 minclk~133 minclk } { 0.000ns 0.819ns 0.209ns 0.221ns 0.000ns } { 0.000ns 0.346ns 0.053ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.262 ns - Smallest " "Info: - Smallest clock skew is -9.262 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.419 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.419 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 12 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 12; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.712 ns) 2.861 ns sound\[0\] 2 REG LCFF_X15_Y8_N9 4 " "Info: 2: + IC(1.295 ns) + CELL(0.712 ns) = 2.861 ns; Loc. = LCFF_X15_Y8_N9; Fanout = 4; REG Node = 'sound\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { clk sound[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.712 ns) 4.058 ns clk_1hz 3 REG LCFF_X18_Y8_N5 3 " "Info: 3: + IC(0.485 ns) + CELL(0.712 ns) = 4.058 ns; Loc. = LCFF_X18_Y8_N5; Fanout = 3; REG Node = 'clk_1hz'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.197 ns" { sound[0] clk_1hz } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.743 ns) + CELL(0.618 ns) 5.419 ns minclk 4 REG LCFF_X14_Y6_N29 2 " "Info: 4: + IC(0.743 ns) + CELL(0.618 ns) = 5.419 ns; Loc. = LCFF_X14_Y6_N29; Fanout = 2; REG Node = 'minclk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.361 ns" { clk_1hz minclk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.896 ns ( 53.44 % ) " "Info: Total cell delay = 2.896 ns ( 53.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.523 ns ( 46.56 % ) " "Info: Total interconnect delay = 2.523 ns ( 46.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.419 ns" { clk sound[0] clk_1hz minclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.419 ns" { clk clk~combout sound[0] clk_1hz minclk } { 0.000ns 0.000ns 1.295ns 0.485ns 0.743ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 14.681 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 14.681 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 12 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 12; CLK Node = 'clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.295 ns) + CELL(0.712 ns) 2.861 ns sound\[0\] 2 REG LCFF_X15_Y8_N9 4 " "Info: 2: + IC(1.295 ns) + CELL(0.712 ns) = 2.861 ns; Loc. = LCFF_X15_Y8_N9; Fanout = 4; REG Node = 'sound\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.007 ns" { clk sound[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.485 ns) + CELL(0.712 ns) 4.058 ns clk_1hz 3 REG LCFF_X18_Y8_N5 3 " "Info: 3: + IC(0.485 ns) + CELL(0.712 ns) = 4.058 ns; Loc. = LCFF_X18_Y8_N5; Fanout = 3; REG Node = 'clk_1hz'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.197 ns" { sound[0] clk_1hz } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(9.367 ns) + CELL(0.000 ns) 13.425 ns clk_1hz~clkctrl 4 COMB CLKCTRL_G12 8 " "Info: 4: + IC(9.367 ns) + CELL(0.000 ns) = 13.425 ns; Loc. = CLKCTRL_G12; Fanout = 8; COMB Node = 'clk_1hz~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "9.367 ns" { clk_1hz clk_1hz~clkctrl } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.638 ns) + CELL(0.618 ns) 14.681 ns sec1\[5\] 5 REG LCFF_X13_Y9_N19 5 " "Info: 5: + IC(0.638 ns) + CELL(0.618 ns) = 14.681 ns; Loc. = LCFF_X13_Y9_N19; Fanout = 5; REG Node = 'sec1\[5\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.256 ns" { clk_1hz~clkctrl sec1[5] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 140 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.896 ns ( 19.73 % ) " "Info: Total cell delay = 2.896 ns ( 19.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "11.785 ns ( 80.27 % ) " "Info: Total interconnect delay = 11.785 ns ( 80.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.681 ns" { clk sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.681 ns" { clk clk~combout sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } { 0.000ns 0.000ns 1.295ns 0.485ns 9.367ns 0.638ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.419 ns" { clk sound[0] clk_1hz minclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.419 ns" { clk clk~combout sound[0] clk_1hz minclk } { 0.000ns 0.000ns 1.295ns 0.485ns 0.743ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.681 ns" { clk sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.681 ns" { clk clk~combout sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } { 0.000ns 0.000ns 1.295ns 0.485ns 9.367ns 0.638ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 140 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.856 ns" { sec1[5] WideNor5~25 WideNor5 minclk~133 minclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.856 ns" { sec1[5] WideNor5~25 WideNor5 minclk~133 minclk } { 0.000ns 0.819ns 0.209ns 0.221ns 0.000ns } { 0.000ns 0.346ns 0.053ns 0.053ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.419 ns" { clk sound[0] clk_1hz minclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.419 ns" { clk clk~combout sound[0] clk_1hz minclk } { 0.000ns 0.000ns 1.295ns 0.485ns 0.743ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "14.681 ns" { clk sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "14.681 ns" { clk clk~combout sound[0] clk_1hz clk_1hz~clkctrl sec1[5] } { 0.000ns 0.000ns 1.295ns 0.485ns 9.367ns 0.638ns } { 0.000ns 0.854ns 0.712ns 0.712ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "mode register register m\[1\] m\[0\] 500.0 MHz Internal " "Info: Clock \"mode\" Internal fmax is restricted to 500.0 MHz between source register \"m\[1\]\" and destination register \"m\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.943 ns + Longest register register " "Info: + Longest register to register delay is 0.943 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns m\[1\] 1 REG LCFF_X14_Y8_N11 29 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y8_N11; Fanout = 29; REG Node = 'm\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[1] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.560 ns) + CELL(0.228 ns) 0.788 ns m~148 2 COMB LCCOMB_X14_Y8_N28 1 " "Info: 2: + IC(0.560 ns) + CELL(0.228 ns) = 0.788 ns; Loc. = LCCOMB_X14_Y8_N28; Fanout = 1; COMB Node = 'm~148'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.788 ns" { m[1] m~148 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 35 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 0.943 ns m\[0\] 3 REG LCFF_X14_Y8_N29 34 " "Info: 3: + IC(0.000 ns) + CELL(0.155 ns) = 0.943 ns; Loc. = LCFF_X14_Y8_N29; Fanout = 34; REG Node = 'm\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { m~148 m[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.383 ns ( 40.62 % ) " "Info: Total cell delay = 0.383 ns ( 40.62 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.560 ns ( 59.38 % ) " "Info: Total interconnect delay = 0.560 ns ( 59.38 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.943 ns" { m[1] m~148 m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.943 ns" { m[1] m~148 m[0] } { 0.000ns 0.560ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode destination 2.512 ns + Shortest register " "Info: + Shortest clock path from clock \"mode\" to destination register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns mode 1 CLK PIN_R22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_R22; Fanout = 3; CLK Node = 'mode'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.618 ns) 2.512 ns m\[0\] 2 REG LCFF_X14_Y8_N29 34 " "Info: 2: + IC(1.064 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X14_Y8_N29; Fanout = 34; REG Node = 'm\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.682 ns" { mode m[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 57.64 % ) " "Info: Total cell delay = 1.448 ns ( 57.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.064 ns ( 42.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[0] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "mode source 2.512 ns - Longest register " "Info: - Longest clock path from clock \"mode\" to source register is 2.512 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.830 ns) 0.830 ns mode 1 CLK PIN_R22 3 " "Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_R22; Fanout = 3; CLK Node = 'mode'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { mode } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(0.618 ns) 2.512 ns m\[1\] 2 REG LCFF_X14_Y8_N11 29 " "Info: 2: + IC(1.064 ns) + CELL(0.618 ns) = 2.512 ns; Loc. = LCFF_X14_Y8_N11; Fanout = 29; REG Node = 'm\[1\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.682 ns" { mode m[1] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.448 ns ( 57.64 % ) " "Info: Total cell delay = 1.448 ns ( 57.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.064 ns ( 42.36 % ) " "Info: Total interconnect delay = 1.064 ns ( 42.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[1] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[0] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[1] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.943 ns" { m[1] m~148 m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "0.943 ns" { m[1] m~148 m[0] } { 0.000ns 0.560ns 0.000ns } { 0.000ns 0.228ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[0] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.512 ns" { mode m[1] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "2.512 ns" { mode mode~combout m[1] } { 0.000ns 0.000ns 1.064ns } { 0.000ns 0.830ns 0.618ns } "" } } } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[0] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { m[0] } { } { } "" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "turn register min1\[2\] register hclk 109.71 MHz 9.115 ns Internal " "Info: Clock \"turn\" has Internal fmax of 109.71 MHz between source register \"min1\[2\]\" and destination register \"hclk\" (period= 9.115 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.069 ns + Longest register register " "Info: + Longest register to register delay is 1.069 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns min1\[2\] 1 REG LCFF_X15_Y6_N21 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X15_Y6_N21; Fanout = 5; REG Node = 'min1\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { min1[2] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 154 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.282 ns) + CELL(0.366 ns) 0.648 ns Equal19~36 2 COMB LCCOMB_X15_Y6_N26 2 " "Info: 2: + IC(0.282 ns) + CELL(0.366 ns) = 0.648 ns; Loc. = LCCOMB_X15_Y6_N26; Fanout = 2; COMB Node = 'Equal19~36'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.648 ns" { min1[2] Equal19~36 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 255 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.213 ns) + CELL(0.053 ns) 0.914 ns Equal19~37 3 COMB LCCOMB_X15_Y6_N18 4 " "Info: 3: + IC(0.213 ns) + CELL(0.053 ns) = 0.914 ns; Loc. = LCCOMB_X15_Y6_N18; Fanout = 4; COMB Node = 'Equal19~37'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.266 ns" { Equal19~36 Equal19~37 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 255 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.155 ns) 1.069 ns hclk 4 REG LCFF_X15_Y6_N19 1 " "Info: 4: + IC(0.000 ns) + CELL(0.155 ns) = 1.069 ns; Loc. = LCFF_X15_Y6_N19; Fanout = 1; REG Node = 'hclk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.155 ns" { Equal19~37 hclk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.574 ns ( 53.70 % ) " "Info: Total cell delay = 0.574 ns ( 53.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.495 ns ( 46.30 % ) " "Info: Total interconnect delay = 0.495 ns ( 46.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { min1[2] Equal19~36 Equal19~37 hclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.069 ns" { min1[2] Equal19~36 Equal19~37 hclk } { 0.000ns 0.282ns 0.213ns 0.000ns } { 0.000ns 0.366ns 0.053ns 0.155ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-7.862 ns - Smallest " "Info: - Smallest clock skew is -7.862 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "turn destination 5.009 ns + Shortest register " "Info: + Shortest clock path from clock \"turn\" to destination register is 5.009 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns turn 1 CLK PIN_P19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_P19; Fanout = 2; CLK Node = 'turn'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { turn } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.712 ns) 2.543 ns fm\[0\] 2 REG LCFF_X13_Y8_N25 10 " "Info: 2: + IC(1.021 ns) + CELL(0.712 ns) = 2.543 ns; Loc. = LCFF_X13_Y8_N25; Fanout = 10; REG Node = 'fm\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { turn fm[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.225 ns) 3.356 ns count1 3 REG LCCOMB_X14_Y6_N12 4 " "Info: 3: + IC(0.588 ns) + CELL(0.225 ns) = 3.356 ns; Loc. = LCCOMB_X14_Y6_N12; Fanout = 4; REG Node = 'count1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.813 ns" { fm[0] count1 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.225 ns) 3.814 ns m_clk 4 COMB LCCOMB_X14_Y6_N14 1 " "Info: 4: + IC(0.233 ns) + CELL(0.225 ns) = 3.814 ns; Loc. = LCCOMB_X14_Y6_N14; Fanout = 1; COMB Node = 'm_clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { count1 m_clk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.206 ns) + CELL(0.053 ns) 4.073 ns ct1 5 COMB LCCOMB_X14_Y6_N24 2 " "Info: 5: + IC(0.206 ns) + CELL(0.053 ns) = 4.073 ns; Loc. = LCCOMB_X14_Y6_N24; Fanout = 2; COMB Node = 'ct1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.259 ns" { m_clk ct1 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.618 ns) 5.009 ns hclk 6 REG LCFF_X15_Y6_N19 1 " "Info: 6: + IC(0.318 ns) + CELL(0.618 ns) = 5.009 ns; Loc. = LCFF_X15_Y6_N19; Fanout = 1; REG Node = 'hclk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.936 ns" { ct1 hclk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.643 ns ( 52.77 % ) " "Info: Total cell delay = 2.643 ns ( 52.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.366 ns ( 47.23 % ) " "Info: Total interconnect delay = 2.366 ns ( 47.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.009 ns" { turn fm[0] count1 m_clk ct1 hclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.009 ns" { turn turn~combout fm[0] count1 m_clk ct1 hclk } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 0.318ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "turn source 12.871 ns - Longest register " "Info: - Longest clock path from clock \"turn\" to source register is 12.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.810 ns) 0.810 ns turn 1 CLK PIN_P19 2 " "Info: 1: + IC(0.000 ns) + CELL(0.810 ns) = 0.810 ns; Loc. = PIN_P19; Fanout = 2; CLK Node = 'turn'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { turn } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.021 ns) + CELL(0.712 ns) 2.543 ns fm\[0\] 2 REG LCFF_X13_Y8_N25 10 " "Info: 2: + IC(1.021 ns) + CELL(0.712 ns) = 2.543 ns; Loc. = LCFF_X13_Y8_N25; Fanout = 10; REG Node = 'fm\[0\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.733 ns" { turn fm[0] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 57 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.588 ns) + CELL(0.225 ns) 3.356 ns count1 3 REG LCCOMB_X14_Y6_N12 4 " "Info: 3: + IC(0.588 ns) + CELL(0.225 ns) = 3.356 ns; Loc. = LCCOMB_X14_Y6_N12; Fanout = 4; REG Node = 'count1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.813 ns" { fm[0] count1 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.233 ns) + CELL(0.225 ns) 3.814 ns m_clk 4 COMB LCCOMB_X14_Y6_N14 1 " "Info: 4: + IC(0.233 ns) + CELL(0.225 ns) = 3.814 ns; Loc. = LCCOMB_X14_Y6_N14; Fanout = 1; COMB Node = 'm_clk'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.458 ns" { count1 m_clk } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.206 ns) + CELL(0.053 ns) 4.073 ns ct1 5 COMB LCCOMB_X14_Y6_N24 2 " "Info: 5: + IC(0.206 ns) + CELL(0.053 ns) = 4.073 ns; Loc. = LCCOMB_X14_Y6_N24; Fanout = 2; COMB Node = 'ct1'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "0.259 ns" { m_clk ct1 } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(7.554 ns) + CELL(0.000 ns) 11.627 ns ct1~clkctrl 6 COMB CLKCTRL_G7 8 " "Info: 6: + IC(7.554 ns) + CELL(0.000 ns) = 11.627 ns; Loc. = CLKCTRL_G7; Fanout = 8; COMB Node = 'ct1~clkctrl'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.554 ns" { ct1 ct1~clkctrl } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.626 ns) + CELL(0.618 ns) 12.871 ns min1\[2\] 7 REG LCFF_X15_Y6_N21 5 " "Info: 7: + IC(0.626 ns) + CELL(0.618 ns) = 12.871 ns; Loc. = LCFF_X15_Y6_N21; Fanout = 5; REG Node = 'min1\[2\]'" { } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.244 ns" { ct1~clkctrl min1[2] } "NODE_NAME" } } { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 154 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.643 ns ( 20.53 % ) " "Info: Total cell delay = 2.643 ns ( 20.53 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "10.228 ns ( 79.47 % ) " "Info: Total interconnect delay = 10.228 ns ( 79.47 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.871 ns" { turn fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.871 ns" { turn turn~combout fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 7.554ns 0.626ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.000ns 0.618ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.009 ns" { turn fm[0] count1 m_clk ct1 hclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.009 ns" { turn turn~combout fm[0] count1 m_clk ct1 hclk } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 0.318ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.871 ns" { turn fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.871 ns" { turn turn~combout fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 7.554ns 0.626ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.000ns 0.618ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 154 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" { } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.069 ns" { min1[2] Equal19~36 Equal19~37 hclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.069 ns" { min1[2] Equal19~36 Equal19~37 hclk } { 0.000ns 0.282ns 0.213ns 0.000ns } { 0.000ns 0.366ns 0.053ns 0.155ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.009 ns" { turn fm[0] count1 m_clk ct1 hclk } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.009 ns" { turn turn~combout fm[0] count1 m_clk ct1 hclk } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 0.318ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.618ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "12.871 ns" { turn fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "12.871 ns" { turn turn~combout fm[0] count1 m_clk ct1 ct1~clkctrl min1[2] } { 0.000ns 0.000ns 1.021ns 0.588ns 0.233ns 0.206ns 7.554ns 0.626ns } { 0.000ns 0.810ns 0.712ns 0.225ns 0.225ns 0.053ns 0.000ns 0.618ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
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