dianzirili.tan.qmsg

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "count1 " "Warning: Node \"count1\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "count4 " "Warning: Node \"count4\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "count3 " "Warning: Node \"count3\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "count2 " "Warning: Node \"count2\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "week\[0\]\$latch " "Warning: Node \"week\[0\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "week\[1\]\$latch " "Warning: Node \"week\[1\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "week\[2\]\$latch " "Warning: Node \"week\[2\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[0\]\$latch " "Warning: Node \"hour\[0\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[1\]\$latch " "Warning: Node \"hour\[1\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[2\]\$latch " "Warning: Node \"hour\[2\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[3\]\$latch " "Warning: Node \"hour\[3\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[4\]\$latch " "Warning: Node \"hour\[4\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[5\]\$latch " "Warning: Node \"hour\[5\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[6\]\$latch " "Warning: Node \"hour\[6\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "hour\[7\]\$latch " "Warning: Node \"hour\[7\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[0\]\$latch " "Warning: Node \"min\[0\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[1\]\$latch " "Warning: Node \"min\[1\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[2\]\$latch " "Warning: Node \"min\[2\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[3\]\$latch " "Warning: Node \"min\[3\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[4\]\$latch " "Warning: Node \"min\[4\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[5\]\$latch " "Warning: Node \"min\[5\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[6\]\$latch " "Warning: Node \"min\[6\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "min\[7\]\$latch " "Warning: Node \"min\[7\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "LD_hour\$latch " "Warning: Node \"LD_hour\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "LD_min\$latch " "Warning: Node \"LD_min\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "LD_mon\$latch " "Warning: Node \"LD_mon\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "LD_day\$latch " "Warning: Node \"LD_day\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "LD_week\$latch " "Warning: Node \"LD_week\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 81 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[0\]\$latch " "Warning: Node \"sec\[0\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[1\]_750 " "Warning: Node \"sec\[1\]_750\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[1\]\$latch " "Warning: Node \"sec\[1\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[2\]\$latch " "Warning: Node \"sec\[2\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[3\]\$latch " "Warning: Node \"sec\[3\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[4\]\$latch " "Warning: Node \"sec\[4\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[5\]\$latch " "Warning: Node \"sec\[5\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[6\]\$latch " "Warning: Node \"sec\[6\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0} { "Warning" "WTDB_COMB_LATCH_NODE" "sec\[7\]\$latch " "Warning: Node \"sec\[7\]\$latch\" is a latch" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 0 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "mode " "Info: Assuming node \"mode\" is an undefined clock" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "mode" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "turn " "Info: Assuming node \"turn\" is an undefined clock" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 28 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "turn" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "33 " "Warning: Found 33 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "count2 " "Info: Detected ripple clock \"count2\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "count2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count3 " "Info: Detected ripple clock \"count3\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "count3" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count4 " "Info: Detected ripple clock \"count4\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "count4" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "count1 " "Info: Detected ripple clock \"count1\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 40 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "count1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux35~36 " "Info: Detected gated clock \"Mux35~36\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 62 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux35~36" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux22~26 " "Info: Detected gated clock \"Mux22~26\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux22~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux3~56 " "Info: Detected gated clock \"Mux3~56\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux3~56" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "num5\[0\] " "Info: Detected ripple clock \"num5\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 111 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "num5\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "ct5 " "Info: Detected gated clock \"ct5\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ct5" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "hclk " "Info: Detected ripple clock \"hclk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "hclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "h_clk " "Info: Detected gated clock \"h_clk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "h_clk" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "num2\[0\] " "Info: Detected ripple clock \"num2\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 90 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "num2\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "ct2 " "Info: Detected gated clock \"ct2\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ct2" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "dclk " "Info: Detected ripple clock \"dclk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "dclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "d_clk " "Info: Detected gated clock \"d_clk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "d_clk" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "num3\[0\] " "Info: Detected ripple clock \"num3\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 97 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "num3\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux37~26 " "Info: Detected gated clock \"Mux37~26\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 62 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux37~26" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "ct3 " "Info: Detected gated clock \"ct3\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ct3" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "monclk " "Info: Detected ripple clock \"monclk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "monclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "num4\[0\] " "Info: Detected ripple clock \"num4\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 104 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "num4\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "mon_clk " "Info: Detected gated clock \"mon_clk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "mon_clk" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "ct4 " "Info: Detected gated clock \"ct4\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ct4" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "Mux0~18 " "Info: Detected gated clock \"Mux0~18\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 240 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux0~18" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fm\[0\] " "Info: Detected ripple clock \"fm\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 57 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "fm\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "minclk " "Info: Detected ripple clock \"minclk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "minclk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "m_clk " "Info: Detected gated clock \"m_clk\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "m_clk" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "num1\[0\] " "Info: Detected ripple clock \"num1\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 82 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "num1\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_GATED_CLK" "ct1 " "Info: Detected gated clock \"ct1\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 41 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "ct1" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "m\[2\] " "Info: Detected ripple clock \"m\[2\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "m\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "m\[1\] " "Info: Detected ripple clock \"m\[1\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "m\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "m\[0\] " "Info: Detected ripple clock \"m\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 53 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "m\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "sound\[0\] " "Info: Detected ripple clock \"sound\[0\]\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 43 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "sound\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "clk_1hz " "Info: Detected ripple clock \"clk_1hz\" as buffer" {  } { { "dianzirili.v" "" { Text "E:/zzs4/dianzirili.v" 38 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk_1hz" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}