dianzirili.map.rpt

用verilog实现的电子日历程序,在Quartus II上编译通过并成功实现

Warning (10230): Verilog HDL assignment warning at dianzirili.v(119): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(120): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(121): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(122): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(123): truncated value with size 2 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(137): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(138): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(151): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(152): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(165): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(166): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(180): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(181): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(188): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(189): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(196): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(197): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(212): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(213): truncated value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(226): truncated value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(236): truncated value with size 32 to match size of target (4)
Warning (10270): Verilog HDL Case Statement warning at dianzirili.v(240): incomplete case statement has no default case item
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable "hour", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable "min", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable "sec", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(240): inferring latch(es) for variable "week", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at dianzirili.v(251): truncated value with size 32 to match size of target (1)
Warning (10030): Net "alert1" at dianzirili.v(39) has no driver or initial value, using a default initial value '0'
Info (10041): Inferred latch for "week[0]" at dianzirili.v(240)
Info (10041): Inferred latch for "week[1]" at dianzirili.v(240)
Info (10041): Inferred latch for "week[2]" at dianzirili.v(240)
Info (10041): Inferred latch for "week[3]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[0]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[1]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[2]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[3]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[4]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[5]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[6]" at dianzirili.v(240)
Info (10041): Inferred latch for "sec[7]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[0]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[1]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[2]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[3]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[4]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[5]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[6]" at dianzirili.v(240)
Info (10041): Inferred latch for "min[7]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[0]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[1]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[2]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[3]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[4]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[5]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[6]" at dianzirili.v(240)
Info (10041): Inferred latch for "hour[7]" at dianzirili.v(240)
Info (10041): Inferred latch for "LD_week" at dianzirili.v(81)
Info (10041): Inferred latch for "LD_day" at dianzirili.v(81)
Info (10041): Inferred latch for "LD_mon" at dianzirili.v(81)
Info (10041): Inferred latch for "LD_hour" at dianzirili.v(81)
Info (10041): Inferred latch for "LD_min" at dianzirili.v(81)
Info (10041): Inferred latch for "count4" at dianzirili.v(81)
Info (10041): Inferred latch for "count3" at dianzirili.v(81)
Info (10041): Inferred latch for "count2" at dianzirili.v(81)
Info (10041): Inferred latch for "count1" at dianzirili.v(81)
Warning: Reduced register "num5[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num4[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num3[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num2[1]" with stuck data_in port to stuck value GND
Warning: Reduced register "num1[1]" with stuck data_in port to stuck value GND
Info: Power-up level of register "wclk" is not specified -- using power-up level of High to minimize register
Warning: Reduced register "wclk" with stuck data_in port to stuck value VCC
Info: Duplicate registers merged to single register
    Info: Duplicate register "fm[1]" merged to single register "fm[0]"
Info: Clock multiplexers have been protected
Info: Duplicate registers merged to single register
    Info: Duplicate register "clk_2hz" merged to single register "sound[0]"
Warning: Latch week[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch week[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch week[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch week[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch hour[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch hour[7]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch min[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch min[7]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch LD_hour$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch LD_min$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[2]
Warning: Latch LD_mon$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch LD_day$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch LD_week$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[1]
Warning: Latch sec[0]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[1]_750 has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[1]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[2]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[3]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[4]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[5]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[6]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Latch sec[7]$latch has unsafe behavior
    Warning: Ports D and ENA on the latch are fed by the same signal m[0]
Warning: Reduced register "week1[3]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "week[3]" stuck at GND
Info: Registers with preset signals will power-up high
Info: 3 registers lost all their fanouts during netlist optimizations. The first 3 are displayed below.
    Info: Register "wm[2]" lost all its fanouts during netlist optimizations.
    Info: Register "wm[1]" lost all its fanouts during netlist optimizations.
    Info: Register "wm[0]" lost all its fanouts during netlist optimizations.
Info: Generated suppressed messages file E:/zzs4/dianzirili.map.smsg
Info: Implemented 234 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 34 output pins
    Info: Implemented 194 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 122 warnings
    Info: Allocated 138 megabytes of memory during processing
    Info: Processing ended: Fri Oct 26 00:14:23 2007
    Info: Elapsed time: 00:00:05


+------------------------------------------+
; Analysis & Synthesis Suppressed Messages ;
+------------------------------------------+
The suppressed messages can be found in E:/zzs4/dianzirili.map.smsg.