📄 dianzirili.map.rpt
字号:
; Maximum fan-out node ; reset ;
; Maximum fan-out ; 47 ;
; Total fan-out ; 864 ;
; Average fan-out ; 2.86 ;
+-----------------------------------------------+-------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
; |dianzirili ; 192 (192) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; 0 ; 40 ; 0 ; |dianzirili ; work ;
+----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+----------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+-----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+-----------------------------------------------------+---------------------+------------------------+
; week[0]$latch ; Mux3 ; yes ;
; week[1]$latch ; Mux3 ; yes ;
; week[2]$latch ; Mux3 ; yes ;
; week[3]$latch ; Mux3 ; yes ;
; hour[0]$latch ; Mux3 ; yes ;
; hour[1]$latch ; Mux3 ; yes ;
; hour[2]$latch ; Mux3 ; yes ;
; hour[3]$latch ; Mux3 ; yes ;
; hour[4]$latch ; Mux3 ; yes ;
; hour[5]$latch ; Mux3 ; yes ;
; hour[6]$latch ; Mux3 ; yes ;
; hour[7]$latch ; Mux3 ; yes ;
; min[0]$latch ; Mux22 ; yes ;
; min[1]$latch ; Mux22 ; yes ;
; min[2]$latch ; Mux22 ; yes ;
; min[3]$latch ; Mux22 ; yes ;
; min[4]$latch ; Mux22 ; yes ;
; min[5]$latch ; Mux22 ; yes ;
; min[6]$latch ; Mux22 ; yes ;
; min[7]$latch ; Mux22 ; yes ;
; LD_hour$latch ; Mux37 ; yes ;
; LD_min$latch ; Mux37 ; yes ;
; LD_mon$latch ; Mux35 ; yes ;
; LD_day$latch ; Mux35 ; yes ;
; LD_week$latch ; Mux32 ; yes ;
; sec[0]$latch ; Mux22 ; yes ;
; sec[1]_750 ; Mux22 ; yes ;
; sec[1]$latch ; Mux22 ; yes ;
; sec[2]$latch ; Mux22 ; yes ;
; sec[3]$latch ; Mux22 ; yes ;
; sec[4]$latch ; Mux22 ; yes ;
; sec[5]$latch ; Mux22 ; yes ;
; sec[6]$latch ; Mux22 ; yes ;
; sec[7]$latch ; Mux22 ; yes ;
; count1 ; fm[0] ; yes ;
; count2 ; fm[0] ; yes ;
; count4 ; fm[0] ; yes ;
; count3 ; fm[0] ; yes ;
; Number of user-specified and inferred latches = 38 ; ; ;
+-----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+---------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+----------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+----------------------------------------+----------------------------------------+
; num5[1] ; Stuck at GND due to stuck port data_in ;
; num4[1] ; Stuck at GND due to stuck port data_in ;
; num3[1] ; Stuck at GND due to stuck port data_in ;
; num2[1] ; Stuck at GND due to stuck port data_in ;
; num1[1] ; Stuck at GND due to stuck port data_in ;
; wclk ; Stuck at VCC due to stuck port data_in ;
; wm[0..2] ; Lost fanout ;
; fm[1] ; Merged with fm[0] ;
; clk_2hz ; Merged with sound[0] ;
; week1[3] ; Stuck at GND due to stuck port data_in ;
; Total Number of Removed Registers = 12 ; ;
+----------------------------------------+----------------------------------------+
+------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+---------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+---------------+---------------------------+----------------------------------------+
; num5[1] ; Stuck at GND ; week1[3] ;
; ; due to stuck port data_in ; ;
; num3[1] ; Stuck at GND ; wclk ;
; ; due to stuck port data_in ; ;
+---------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 70 ;
; Number of registers using Synchronous Clear ; 8 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 43 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 3 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; week1[0] ; 4 ;
; mon1[0] ; 13 ;
; day1[0] ; 9 ;
; Total number of inverted registers = 3 ; ;
+----------------------------------------+---------+
+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1 ; 4 bits ; 8 ALUTs ; 8 ALUTs ; 0 ALUTs ; Yes ; |dianzirili|sec1[3] ;
; 3:1 ; 4 bits ; 8 ALUTs ; 8 ALUTs ; 0 ALUTs ; Yes ; |dianzirili|min1[0] ;
; 3:1 ; 3 bits ; 6 ALUTs ; 6 ALUTs ; 0 ALUTs ; Yes ; |dianzirili|mon1[1] ;
; 3:1 ; 4 bits ; 8 ALUTs ; 8 ALUTs ; 0 ALUTs ; Yes ; |dianzirili|hour1[1] ;
; 6:1 ; 4 bits ; 16 ALUTs ; 4 ALUTs ; 12 ALUTs ; Yes ; |dianzirili|day1[4] ;
; 5:1 ; 3 bits ; 9 ALUTs ; 6 ALUTs ; 3 ALUTs ; Yes ; |dianzirili|day1[3] ;
; 4:1 ; 8 bits ; 16 ALUTs ; 16 ALUTs ; 0 ALUTs ; No ; |dianzirili|Mux8 ;
; 4:1 ; 8 bits ; 16 ALUTs ; 16 ALUTs ; 0 ALUTs ; No ; |dianzirili|Mux30 ;
; 5:1 ; 8 bits ; 24 ALUTs ; 16 ALUTs ; 8 ALUTs ; No ; |dianzirili|Mux21 ;
; 4:1 ; 4 bits ; 8 ALUTs ; 4 ALUTs ; 4 ALUTs ; No ; |dianzirili|Mux5 ;
; 4:1 ; 2 bits ; 4 ALUTs ; 4 ALUTs ; 0 ALUTs ; No ; |dianzirili|Mux34 ;
; 4:1 ; 2 bits ; 4 ALUTs ; 4 ALUTs ; 0 ALUTs ; No ; |dianzirili|Mux38 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 7.1 Build 156 04/30/2007 SJ Full Version
Info: Processing started: Fri Oct 26 00:14:18 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dianzirili -c dianzirili
Info: Found 1 design units, including 1 entities, in source file dianzirili.v
Info: Found entity 1: dianzirili
Info: Elaborating entity "dianzirili" for the top level hierarchy
Warning (10858): Verilog HDL warning at dianzirili.v(39): object alert1 used but never assigned
Warning (10230): Verilog HDL assignment warning at dianzirili.v(47): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(54): truncated value with size 32 to match size of target (3)
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "count1", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "count2", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "count3", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "count4", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "LD_min", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "LD_hour", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "LD_mon", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "LD_day", which holds its previous value in one or more paths through the always construct
Warning (10240): Verilog HDL Always Construct warning at dianzirili.v(81): inferring latch(es) for variable "LD_week", which holds its previous value in one or more paths through the always construct
Warning (10230): Verilog HDL assignment warning at dianzirili.v(87): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(94): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(101): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(108): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at dianzirili.v(115): truncated value with size 32 to match size of target (2)
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -