adcchbak.v

FPGA verilog

module ADCCh
	(
		CLK,
		InputAD,
		OutputAD
	);

	input				CLK;
	input	[11:0]		InputAD;
	output	[11:0]		OutputAD;
	
	reg		[11:0]		InputADReg;
	reg 	[11:0]		OutputAD;	
	
	reg		[16:0]	AccResult;
	wire	[16:0]	ParamResult,Result;
		

	reg		[11:0]	Input0,Input1,Input2,Input3,Input4,Input5,Input6,Input7;
	reg		[11:0]	Input8,Input9,Input10,Input11,Input12,Input13,Input14,Input15;
	reg		[11:0]	Input16,Input17,Input18,Input19,Input20,Input21,Input22,Input23;
	reg		[11:0]	Input24,Input25,Input26,Input27,Input28,Input29,Input30,Input31;
	
	lpm_add_signed_17	ParamAcc(.dataa(AccResult),
							.datab(ParamResult),
							.result(Result));

	lpm_sub_signed_17	ParamSub(.dataa({5'b00000,InputADReg}),
							.datab({5'b00000,Input31}),
							.result(ParamResult));
							
	always @(posedge CLK)
	begin
		InputADReg <= InputAD;	
	end

	always @(posedge CLK)
	begin
		 OutputAD <= AccResult[16:5];
	end

	always @(posedge CLK)
	begin
		AccResult <= Result;
	end
	
	always @(posedge CLK)
	begin
		Input0 <= InputADReg;
		Input1 <= Input0;
		Input2 <= Input1;
		Input3 <= Input2;
		Input4 <= Input3;
		Input5 <= Input4;
		Input6 <= Input5;
		Input7 <= Input6;
		Input8 <= Input7;
		Input9 <= Input8;
		Input10 <= Input9;
		Input11 <= Input10;
		Input12 <= Input11;
		Input13 <= Input12;
		Input14 <= Input13;
		Input15 <= Input14;
		Input16 <= Input15;
		Input17 <= Input16;
		Input18 <= Input17;
		Input19 <= Input18;
		Input20 <= Input19;
		Input21 <= Input20;
		Input22 <= Input21;
		Input23 <= Input22;
		Input24 <= Input23;
		Input25 <= Input24;
		Input26 <= Input25;
		Input27 <= Input26;
		Input28 <= Input27;
		Input29 <= Input28;
		Input30 <= Input29;
		Input31 <= Input30;
	end
	
endmodule