feeddata.v

来自「FPGA verilog」· Verilog 代码 · 共 55 行

module FeedData
	(
		CLK,
		InputPwr,
		TargetPwr,
		FeedDataOut
	);

	input			CLK;
	input	[31:0]	InputPwr;
	input	[31:0]	TargetPwr;
	output	[11:0]	FeedDataOut;

	wire	[31:0]	Gain,Result0,Result1,Result2,Result3,Result4;
	
	lpm_sub0	b2v_inst1(.dataa(TargetPwr),
					.datab(InputPwr),
					.result(Gain));
	

	//x(x(0.961216305x -19.29016918) +180.8325714) -420.8460675	
	
	lpm_mult2	b2v_inst1(.dataa({6'h00,Gain[31:6]}),//Q9
					.datab(32'd31497),//0.961216305
					.result(Result0));//Q9

	lpm_sub0	b2v_inst2(.dataa(Result0),
					.datab(32'd9877),//19.29016918
					.result(Result1));

	lpm_mult2	b2v_inst3(.dataa(Result1),
					.datab(Gain),
					.result(Result2));//Q9

	lpm_add0	b2v_inst4(.dataa(Result2),
					.datab(32'd92586),//180.8325714
					.result(Result3));

	lpm_mult2	b2v_inst5(.dataa(Result3),
					.datab(Gain),
					.result(Result4));//Q9
	
	lpm_sub0	b2v_inst6(.dataa(Result0),
					.datab(32'd9877),//19.29016918
					.result(Result1));
	
//	always @(Gain)
//	begin
//		if (Gain>655360)
//		begin
//			
//		end
//	end
endmodule