lopovermonitor.v

来自「FPGA verilog」· Verilog 代码 · 共 72 行

module LopOverMonitor
	(
		CLK,
		Param,
		LIM_Set,
		LIM_Output
	);
	input 			EN;
	input 			CLK;
	input	[31:0]	Param,
					LIM_Set;
	output 			LIM_Output;
	
	reg 			LimReg;
	reg				Lim;
	reg		[31:0]	RaiseTime,ResumeTime;
	
	integer		iThr,
				iParam0;

	assign LIM_Output = LimReg;
	
	always @(Param or LIM_Set)
	begin
		iParam0 = Param;
		iThr = LIM_Set;
		if (iParam0>iThr)
			Lim = 1'b1;
		else
			Lim = 1'b0;
	end
	
	always @(posedge CLK)
	begin
		if (Lim)
		begin
			if (RaiseTime[31]!=1)
				RaiseTime <= RaiseTime + 1'b1;
		end
		else if (ResumeTime>32'd20)//1us
			RaiseTime <= 32'h00000000;
	end

	always @(posedge CLK)
	begin
		if (!Lim)
		begin
			if (ResumeTime[31]!=1)
				ResumeTime <= ResumeTime + 1'b1;
		end
		else if (RaiseTime>32'd20)
			ResumeTime <= 32'h00000000;
	end
	
	always @(posedge CLK)
	begin
		if (EN)
		begin
			if (Lim)
			begin
				if (RaiseTime>32'd16000)//800us
					LimReg <= 1'b1;
			end
			else begin
				if (ResumeTime>32'd16000)
					LimReg <= 1'b0;
			end
		end
	end
	
endmodule