ms_clock.v

FPGA verilog

module MS_Clock
	(
		CLK,
		MS_Single
	);

	input	CLK;
	output	MS_Single;

	reg		MS_Single;
	
	reg		[16:0] 	Counter;

	always @(posedge CLK)
	begin
		if (Counter==16'd10000)
			MS_Single <= 1'b1;
		else
			MS_Single <= 1'b0;
	end
endmodule