led.v

FPGA verilog

module LED
	(
		EN,
		CLK,
		LED
	);

	input		EN;
	input		CLK;
	output		LED;

	reg			LED;

	reg[31:0]	Ledcount;
	
	
	always @(posedge CLK)
	begin
		if (EN)
		begin
			if (Ledcount==32'd10000000)
			begin
				Ledcount <=0;
				LED <= ~LED;
			end
			else
				Ledcount <= Ledcount+1'b1;
		end
		else
			LED <=1'b1;
	end

endmodule