ltgt0alarmmonitor.v

FPGA verilog

module LTGT0AlarmMonitor
	(
		EN,
		SYS_CLK,
		Param,
		Debounce_Time_Set,
		THR_H_Set,
		HYS_H_Set,
		THR_L_Set,
		HYS_L_Set,
		Alarm_Output
	);
	
	input 			EN;
	input 			SYS_CLK;
	input	[31:0]	Param,
					THR_H_Set,
					HYS_H_Set,
					THR_L_Set,
					HYS_L_Set;
	input	[31:0]	Debounce_Time_Set;
	output 			Alarm_Output;
	
	reg 			AlarmReg;
	reg				Alarm;
	reg				ResumeAlarm;
	reg		[31:0]	RaiseTime,ResumeTime;
	
	wire	[31:0]	Hys_H,Hys_L;

	integer 		iParam0,
					iParam1,
					iTHR_H_Set,
					iHys_H,
					iTHR_L_Set,
					iHys_L;
	
	lpm_sub_signed_32 Hyssub(.dataa(THR_H_Set),
						.datab(HYS_H_Set),
						.result(Hys_H));

	lpm_add_signed_32 Hysadd(.dataa(THR_L_Set),
						.datab(HYS_L_Set),
						.result(Hys_L));

	assign Alarm_Output = AlarmReg;
	
	always @(Param or THR_H_Set or THR_L_Set)
	begin
		iParam0 = Param;
		iTHR_H_Set = THR_H_Set;
		iTHR_L_Set = THR_L_Set;
		if ((iParam0>iTHR_H_Set)||(iParam0<iTHR_L_Set))
			Alarm = 1'b1;
		else
			Alarm = 1'b0;
	end

	always @(Param or Hys_H or Hys_L)
	begin
		iParam1 = Param;
		iHys_H = Hys_H;
		iHys_L = Hys_L;
		if ((iParam1<iHys_H)&&(iParam1>iHys_L))
			ResumeAlarm = 1'b1;
		else
			ResumeAlarm = 1'b0;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (Alarm)
		begin
			if (RaiseTime[31]!=1)
				RaiseTime <= RaiseTime + 1'b1;
		end
		else if (ResumeTime>32'd2)
			RaiseTime <= 32'h00000000;
	end

	always @(posedge SYS_CLK)
	begin
		if (!Alarm)
		begin
			if (ResumeTime[31]!=1)
				ResumeTime <= ResumeTime + 1'b1;
		end
		else if (RaiseTime>32'd2)
			ResumeTime <= 32'h00000000;
	end
	
	always @(posedge SYS_CLK)
	begin
		if (EN)
		begin
			if (Alarm)
			begin
				if (RaiseTime>32'd400000)
					AlarmReg <= 1'b1;
			end
			else begin
				if (ResumeAlarm)
				begin
					if (ResumeTime>Debounce_Time_Set)
						AlarmReg <= 1'b0;
				end
			end
		end
	end
	
endmodule