syncread.v

FPGA verilog

module SyncRead
	(
		RD,
		CLK,
		InputPwrIn,
		OutputPwrIn,
		VOAInputPwrIn,
		VOAOutputPwrIn,
		VOAAttIn,
		RFLPwrIn,
		RFLADIn,
		GainIn,
		POutsigIn,
		InputPwrADIn,
		OutputPwrADIn,
		VOAInputADIn,
		VOAOutputADIn,
		PumpDacIn,
		HrsIn,
		IldmIn,
		
		InputPwrOut,
		OutputPwrOut,
		VOAInputPwrOut,
		VOAOutputPwrOut,
		VOAAttOut,
		RFLPwrOut,
		RFLADOut,
		GainOut,
		POutsigOut,
		InputPwrADOut,
		OutputPwrADOut,
		VOAInputADOut,
		VOAOutputADOut,
		PumpDacOut,
		HrsOut,
		IldmOut
	);
	
	input			RD;
	input			CLK;
	input	[31:0]	InputPwrIn;
	input	[31:0]	OutputPwrIn;
	input	[31:0]	VOAInputPwrIn;
	input	[31:0]	VOAOutputPwrIn;
	input	[31:0]	VOAAttIn;
	input	[31:0]	RFLPwrIn;
	input	[11:0]	RFLADIn;
	input	[31:0]	GainIn;
	input	[31:0]	POutsigIn;
	input	[11:0]	InputPwrADIn;
	input	[11:0]	OutputPwrADIn;
	input	[11:0]	VOAInputADIn;
	input	[11:0]	VOAOutputADIn;
	input	[11:0]	PumpDacIn;
	input	[31:0]	HrsIn;
	input	[31:0]	IldmIn;
	


	output	[31:0]	InputPwrOut;
	output	[31:0]	OutputPwrOut;
	output	[31:0]	VOAInputPwrOut;
	output	[31:0]	VOAOutputPwrOut;
	output	[31:0]	VOAAttOut;
	output	[31:0]	RFLPwrOut;
	output	[11:0]	RFLADOut;

	output	[31:0]	GainOut;
	output	[31:0]	POutsigOut;
	output	[11:0]	InputPwrADOut;
	output	[11:0]	OutputPwrADOut;
	output	[11:0]	VOAInputADOut;
	output	[11:0]	VOAOutputADOut;
	output	[11:0]	PumpDacOut;
	output	[31:0]	HrsOut;
	output	[31:0]	IldmOut;


	assign	InputPwrOut =InputPwrIn;
	assign	OutputPwrOut =OutputPwrIn;
	assign	VOAInputPwrOut =VOAInputPwrIn;
	assign	VOAOutputPwrOut =VOAOutputPwrIn;
	assign	VOAAttOut = VOAAttIn;
	assign	RFLPwrOut = RFLPwrIn;
	assign	RFLADOut = RFLADIn;
	assign	GainOut = GainIn;
	assign	POutsigOut = POutsigIn;
	assign	InputPwrADOut = InputPwrADIn;
	assign	OutputPwrADOut = OutputPwrADIn;
	assign	VOAInputADOut = VOAInputADIn;
	assign	VOAOutputADOut = VOAOutputADIn;
	assign	PumpDacOut = PumpDacIn;

	assign	HrsOut = HrsIn;
	assign	IldmOut = IldmIn;

/*

	reg		[31:0]	InputPwrInreg;
	reg		[31:0]	OutputPwrInreg;
	reg		[31:0]	VOAInputPwrInreg;
	reg		[31:0]	VOAOutputPwrInreg;
	reg		[31:0]	VOAAttInreg;
	reg		[31:0]	RFLPwrInreg;
	reg		[11:0]	RFLADInreg;
	reg		[31:0]	GainInreg;
	reg		[31:0]	POutsigInreg;
	reg		[11:0]	InputPwrADInreg;
	reg		[11:0]	OutputPwrADInreg;
	reg		[11:0]	VOAInputADInreg;
	reg		[11:0]	VOAOutputADInreg;
	reg		[11:0]	PumpDacInreg;
	reg		[31:0]	HrsInreg;
	reg		[31:0]	IldmInreg;

	reg		[31:0]	InputPwrOut;
	reg		[31:0]	OutputPwrOut;
	reg		[31:0]	VOAInputPwrOut;
	reg		[31:0]	VOAOutputPwrOut;
	reg		[31:0]	VOAAttOut;
	reg		[31:0]	RFLPwrOut;
	reg		[11:0]	RFLADOut;
	
	reg		[31:0]	GainOut;
	reg		[31:0]	POutsigOut;
	reg		[11:0]	InputPwrADOut;
	reg		[11:0]	OutputPwrADOut;
	reg		[11:0]	VOAInputADOut;
	reg		[11:0]	VOAOutputADOut;
	reg		[11:0]	PumpDacOut;
	reg		[31:0]	HrsOut;
	reg		[31:0]	IldmOut;

	reg		[31:0]	HrsOut0;
	reg		[31:0]	IldmOut0;

	reg		[31:0]	InputPwrOut0;
	reg		[31:0]	OutputPwrOut0;
	reg		[31:0]	VOAInputPwrOut0;
	reg		[31:0]	VOAOutputPwrOut0;
	reg		[31:0]	VOAAttOut0;
	reg		[31:0]	RFLPwrOut0;
	reg		[11:0]	RFLADOut0;
	
	reg		[31:0]	GainOut0;
	reg		[31:0]	POutsigOut0;
	reg		[11:0]	InputPwrADOut0;
	reg		[11:0]	OutputPwrADOut0;
	reg		[11:0]	VOAInputADOut0;
	reg		[11:0]	VOAOutputADOut0;
	reg		[11:0]	PumpDacOut0;
	
	reg		[7:0]	Counter;
	
	wire	EnableUpdate;
	
	assign 	EnableUpdate = Counter[7]==1'b1;

	always @(posedge CLK)
	begin
		if (RD)
		begin
			if (!EnableUpdate)
				Counter <= Counter+ 1'b1;
		end
		else
			Counter<=8'b0000000;
	end
	
	always @(posedge CLK)
	begin
		HrsInreg <= HrsIn;
		IldmInreg <= IldmIn;
		
		InputPwrInreg <=InputPwrIn;
		OutputPwrInreg <=OutputPwrIn;
		VOAInputPwrInreg <=VOAInputPwrIn;
		VOAOutputPwrInreg <=VOAOutputPwrIn;
		VOAAttInreg <= VOAAttIn;
		RFLPwrInreg <= RFLPwrIn;
		RFLADInreg <= RFLADIn;
		GainInreg <= GainIn;
		POutsigInreg <= POutsigIn;
		InputPwrADInreg <= InputPwrADIn;
		OutputPwrADInreg <= OutputPwrADIn;
		VOAInputADInreg <= VOAInputADIn;
		VOAOutputADInreg <= VOAOutputADIn;
		PumpDacInreg <= PumpDacIn;
	end
		
	always @(posedge CLK)
	begin
		if (EnableUpdate)
		begin
			InputPwrOut <=InputPwrOut0;
			OutputPwrOut <=OutputPwrOut0;
			VOAInputPwrOut <=VOAInputPwrOut0;
			VOAOutputPwrOut <=VOAOutputPwrOut0;
			VOAAttOut <= VOAAttOut0;
			RFLPwrOut <= RFLPwrOut0;
			RFLADOut <= RFLADOut0;
			GainOut <= GainOut0;
			POutsigOut <= POutsigOut0;
			InputPwrADOut <= InputPwrADOut0;
			OutputPwrADOut <= OutputPwrADOut0;
			VOAInputADOut <= VOAInputADOut0;
			VOAOutputADOut <= VOAOutputADOut0;
			PumpDacOut <= PumpDacOut0;

			HrsOut <= HrsOut0;
			IldmOut <= IldmOut0;
		end
	end

	always @(posedge CLK)
	begin
		if (EnableUpdate)
		begin
			HrsOut0 <= HrsInreg;
			IldmOut0 <= IldmInreg;
			
			InputPwrOut0 <=InputPwrInreg;
			OutputPwrOut0 <=OutputPwrInreg;
			VOAInputPwrOut0 <=VOAInputPwrInreg;
			VOAOutputPwrOut0 <=VOAOutputPwrInreg;
			VOAAttOut0 <= VOAAttInreg;
			RFLPwrOut0 <= RFLPwrInreg;
			RFLADOut0 <= RFLADInreg;
			GainOut0 <= GainInreg;
			POutsigOut0 <= POutsigInreg;
			InputPwrADOut0 <= InputPwrADInreg;
			OutputPwrADOut0 <= OutputPwrADInreg;
			VOAInputADOut0 <= VOAInputADInreg;
			VOAOutputADOut0 <= VOAOutputADInreg;
			PumpDacOut0 <= PumpDacInreg;
		end
	end
*/
endmodule