agcctrl.v

FPGA verilog

module AGCCtrl
(
	EN, 
	CLK, 
	WR, 
	SetGain,
	Feed_K_Set,
	Feed_B_Set,
	AddrBus, 
	DataBus, 
	InputPwrAD, 
	OutputPwrAD, 
	Input_Samp_Start,
	Output_Samp_Start,
	A,
	B,
	Gain,
	POutsig, 
	Gain_Disp,
	POutsig_Disp,	
	InputPwrAsmW,
	OutputPwrAsmW,
	FeedForwardData);
	
	input 					EN;
	input 					CLK;
	input 					WR;
	input					SetGain;
	input 	[15:0] 			AddrBus;
	input 	[31:0] 			DataBus;
	input 	[11:0] 			InputPwrAD;
	input 	[11:0] 			OutputPwrAD;
	input 	[10:0]			Input_Samp_Start;
	input 	[10:0]			Output_Samp_Start;
	input	[31:0]			Feed_K_Set, 
							Feed_B_Set;

	input 	[31:0]			A;
	input 	[31:0]			B;
	output 	[31:0] 			Gain;
	output 	[31:0] 			POutsig;
	output 	[31:0] 			Gain_Disp;
	output 	[31:0] 			POutsig_Disp;
	output	[31:0]			InputPwrAsmW;
	output	[31:0]			OutputPwrAsmW;
	output 	[11:0] 			FeedForwardData;

	reg 	[31:0] 			POutsig;
	wire 	[31:0] 			Sig;
	wire	[11:0]			OutputDac;
	
	reg		[31:0]			GainReg;
	
	wire	[23:0]			InputPwr;
	wire	[23:0]			OutputPwr;
	wire	[31:0]			GainResult;
	
	reg		[10:0]			InputPwrADReg;
	reg		[10:0]			OutputPwrADReg;
	
	wire	[12:0]			Result0,Result1;
	wire	[48:0]			Result2;
	wire	[31:0]			Result3;
	
	reg		[23:0]			InputPwr0,OutputPwr0;
	reg		[11:0]			OutputDac0;
	
	reg						SetGainReg;
	wire					SetInputPwr,
							SetInputToDac,
							SetOutputPwr,
							SetEN;
	
	wire					FeedDataSet_Clk;
	wire	[10:0]			FeedDataSet_Addr;
	wire	[11:0]			FeedDataSet_Data;
	
	wire	[10:0]			Input_Addr;
	reg		[10:0]			AddrCounter;
	
	
	assign InputPwrAsmW = {8'h00,InputPwr0};
	assign OutputPwrAsmW = {8'h00,OutputPwr0};
	
	lpm_ram_24x2048 InputPwrmW(
				.data(DataBus[23:0]),
				.wren(SetInputPwr),
				.wraddress(AddrBus[12:2]),
				.rdaddress(Input_Addr),
				.wrclock(~WR),
				.rdclock(CLK),
				.q(InputPwr));

	lpm_ram_12x2048 InputToDac(
				.data(FeedDataSet_Data),
				.wren(SetGain|SetInputToDac),
				.wraddress(FeedDataSet_Addr),
				.rdaddress(InputPwrADReg),
				.wrclock(FeedDataSet_Clk),
				.rdclock(CLK),
				.q(OutputDac));

	lpm_ram_24x2048 OutputPwrmW(
				.data(DataBus[23:0]),
				.wren(SetOutputPwr),
				.wraddress(AddrBus[12:2]),
				.rdaddress(OutputPwrADReg),
				.wrclock(~WR),
				.rdclock(CLK),
				.q(OutputPwr));

	 Gain GainCalc(
				.CLK(CLK),
				.Pin(InputPwr),
				.Pout(OutputPwr),
				.A(A),
				.B(B),
				.Result(GainResult));

	//Psig = Pin*Gain
	PSig	PsigCalc(
				.CLK(CLK),
				.Gain(GainReg),
				.InputPwr(InputPwr0),
				.Result(Sig));

	lpm_sub_signed_13 sub0(
				.dataa({1'b0,InputPwrAD}),
				.datab({2'b00,Input_Samp_Start}),
				.result(Result0));

	lpm_sub_signed_13 sub1(
				.dataa({1'b0,OutputPwrAD}),
				.datab({2'b00,Output_Samp_Start}),
				.result(Result1));

	PwrFilter	PsigFilter(
					.CLK(CLK),
					.InputData(POutsig),
					.OutputData(POutsig_Disp));

	PwrFilter	GainFilter(
					.CLK(CLK),
					.InputData(GainReg),
					.OutputData(Gain_Disp));

	lpm_mult_signed_32x32_hard	b2v_inst2(.dataa({8'h00,InputPwr}),
					.datab(Feed_K_Set),
					.result(Result2));
					
	lpm_add_signed_32 add0(
				.dataa(Result2[31:0]),
				.datab(Feed_B_Set),
				.result(Result3));
	
	assign SetEN = (~EN)&(AddrBus[1:0]==2'b11);
	
	assign SetInputPwr = (AddrBus[15:13]==3'b101)&SetEN;

	assign SetInputToDac = (AddrBus[15:13]==3'b110)&SetEN;

	assign SetOutputPwr = (AddrBus[15:13]==3'b111)&SetEN;

	assign Gain = GainReg;
	
	assign FeedForwardData = OutputDac0;

	assign FeedDataSet_Addr = SetGainReg?AddrCounter:AddrBus[12:2];
	assign FeedDataSet_Data = SetGainReg?Result3[20:9]:DataBus[11:0];
	assign FeedDataSet_Clk = SetGainReg?CLK:(~WR);
	assign Input_Addr = SetGainReg?AddrCounter:InputPwrADReg;

	always @(posedge CLK)
	begin
		if (WR)
			SetGainReg <= SetGain;
	end
	
	always @(posedge CLK)
	begin
		if (SetGainReg)
			begin
				if (AddrCounter!=11'b11111111111)
					AddrCounter <= AddrCounter + 1'b1;
			end
		else
			AddrCounter <= 11'b00000000000;
	end
	
	always @(posedge CLK)
	begin
		InputPwr0 <= InputPwr;
		OutputPwr0 <= OutputPwr;
		OutputDac0 <= OutputDac;
		POutsig <= Sig;
		GainReg <= GainResult;
	end
	
	always @(Result0)
	begin
		if (Result0[12]==1)
			InputPwrADReg <= 11'd0;
		else if (Result0[11]==1)
			InputPwrADReg <= 11'd2047;
		else
			InputPwrADReg <= Result0[10:0];
	end

	always @(Result1)
	begin
		if (Result1[12]==1)
			OutputPwrADReg <= 11'd0;
		else if (Result1[11]==1)
			OutputPwrADReg <= 11'd2047;
		else
			OutputPwrADReg <= Result1[10:0];
	end
endmodule